NXP Semiconductors
Data Sheet: Technical Data
Document Number LS1043A
Rev. 1, 06/2016
QorIQ LS1043A, LS1023A
Data Sheet
Features
• LS1043A contains 32-bit /64-bit ARM® Cortex®-A53
MPCore Processor with the following capabilities:
– Speed up to 1.6 GHz
– 32 KB L1 Instruction Cache w/parity
– 32 KB L1 Data Cache w/ECC
– Neon SIMD Co-processor
– ARM v8 Cryptography Extensions
• 1 MB unified I/D L2 Cache w/ECC
• Hierarchical interconnect fabric
– Hardware Managed Data coherency
– Up to 400 MHz operation
• One 32-bit DDR3L/DDR4 SDRAM memory controller
– ECC and interleaving support
– Up to 1.6 GT/s
• Data Path Acceleration Architecture (DPAA)
incorporating acceleration for the following functions:
– Packet parsing, classification, and distribution
(FMan)
– Queue management for scheduling, packet
sequencing, and congestion management (QMan)
– Hardware buffer management for buffer allocation
and de-allocation (BMan)
– Cryptography acceleration (SEC)
• Parallel Ethernet interfaces
– Up to two RGMII interfaces
– IEEE 1588 support
LS1043A
• Four SerDes lanes for high-speed peripheral interfaces
– Three PCI Express 2.0 controllers supporting x4
operation
– One Serial ATA (SATA 3.0) controller
– Up to four SGMII supporting 1000 Mbit/s
– Up to two SGMII supporting 2500 Mbit/s
– Up to one XFI (10 GbE) interface
– Up to one QSGMII
– Supports 1000Base-KX
• Additional peripheral interfaces
– One Quad Serial Peripheral Interface (QSPI)
controller, one Deserial Serial Peripheral Interface
(DSPI) controller
– Integrated Flash Controller (IFC) supporting NAND
and NOR flash with 28-bit addressing and 16-bit
data
– Three USB 3.0 controllers with integrated PHY
– Enhanced Secure Digital Host Controller (eSDHC)
supporting SD 3.0, eMMC 4.4, and eMMC 4.5
modes
– uQE supporting TDM/HDLC
– Four I2C controllers
– Two 16550 compliant DUARTs and six low-power
UARTs (LPUARTs)
– General Purpose IO (GPIO), eight Flextimers, five
Watchdog timer, four independent PWM/counters/
timer
– Trust Architecture
– Debug supporting run control, data acquisition,
high-speed trace, and performance/event monitoring
NXP reserves the right to change the production detail specifications as may be
required to permit improvements in the design of its products.
Table of Contents
1 Introduction.......................................................................................... 3
2 Pin assignments.................................................................................... 4
2.1
2.2
2.3
2.4
621 ball layout diagrams........................................................... 4
Pinout list (21x21)..................................................................... 10
780 ball layout diagrams........................................................... 47
Pinout list (23x23)..................................................................... 54
3.17 Flextimer interface.....................................................................181
3.18 SPI interface.............................................................................. 184
3.19 QuadSPI interface......................................................................186
3.20 Enhanced secure digital host controller (eSDHC).....................188
3.21 JTAG controller.........................................................................197
3.22 I2C interface.............................................................................. 200
3.23 GPIO interface...........................................................................203
3.24 GIC interface............................................................................. 207
3.25 High-speed serial interfaces (HSSI).......................................... 209
4 Hardware design considerations...........................................................231
4.1
4.2
System clocking........................................................................ 232
Connection recommendations................................................... 241
3 Electrical characteristics.......................................................................96
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
Overall DC electrical characteristics......................................... 96
Power sequencing......................................................................104
Power down requirements......................................................... 106
Power characteristics................................................................. 106
Low power mode saving estimation..........................................110
I/O power dissipation................................................................ 111
Power-on ramp rate................................................................... 113
Input clocks............................................................................... 113
RESET initialization..................................................................120
5 Thermal................................................................................................ 246
5.1
5.2
5.3
Recommended thermal model...................................................248
Temperature diode.....................................................................248
Thermal management information............................................ 248
3.10 DDR4 and DDR3L SDRAM controller.................................... 121
3.11 Ethernet interface, Ethernet management interface, IEEE Std
1588........................................................................................... 127
3.12 QUICC engine specifications.................................................... 152
3.13 USB 3.0 interface...................................................................... 157
3.14 Integrated Flash Controller........................................................161
3.15 LPUART interface.....................................................................178
3.16 DUART interface...................................................................... 180
6 Package information.............................................................................251
6.1
6.2
Package parameters for the FC-PBGA......................................251
Mechanical dimensions of the FC-PBGA................................. 251
7 Security fuse processor.........................................................................254
8 Ordering information............................................................................254
8.1
8.2
Part numbering nomenclature....................................................254
Part marking ............................................................................. 255
9 Revision history....................................................................................256
QorIQ LS1043A, LS1023A Data Sheet, Rev. 1, 06/2016
2
NXP Semiconductors
Introduction
1 Introduction
LS1043A is a cost-effective, power-efficient, and highly integrated system-on-chip (SoC)
design that extends the reach of the NXP value-performance line of QorIQ
communications processors. Featuring extremely power-efficient 64-bit ARM®
Cortex®-A53 cores with ECC-protected L1 and L2 cache memories for high reliability,
running up to 1.6 GHz.
This chip can be used for networking and wireless access points, industrial gateways,
industrial automation, M2M for enterprise, consumer networking and router applications.
This figure shown below represents the block diagram of the LS1043A chip.
ARM
®
ARM Cortex-
Cortex
®
-A53
ARM Cortex-
64-bit Core
A53 64b Cores
A53 ARMCores
64b Cortex-
A53 64b Cores
ARM Cortex-
32 KB
32 KB
D-Cache
32 KB
32 KB
A53 64b32 KB
Cores
I-Cache
32 KB
I-Cache
D-Cache
I-Cache
D-Cache
32 KB
32 KB
I-Cache
D-Cache
1 MB L2 - Cache
32-bit
DDR3L/4
Memory Controller
Secure Boot
Trust Zone
Power Management
IFC, QuadSPI, SPI
SD/SDIO/eMMC
DMA
2x DUART
4x I2C, GPIO
8x FlexTimer
3x USB3.0 w/PHY
6x LPUART
DPAA Hardware
4-Lane 10 GHz SerDes
Buffer
Manager
1G
1G
1G
1G
1G
1/2.5G
Security
Engine
(SEC)
CCI-400™ Coherency Fabric
SMMUs
Real Time Debug
Queue
Manager
Frame Manager
PCIe 2.0
PCIe 2.0
PCIe 2.0
SATA 3.0
uQE
Parse, classify,
distribute
Watchpoint
Cross
Trigger
Perf
Monitor
Trace
1/2.5/10G
Core Complex
Accelerators and Memory Control
Basic Peripherals, Interconnect and Debug
Networking Elements
Figure 1. LS1043A Block Diagram
QorIQ LS1043A, LS1023A Data Sheet, Rev. 1, 06/2016
NXP Semiconductors
3
Pin assignments
This figure shown below represents the block diagram of the LS1023A chip.
ARM®
ARM Cortex-
Cortex®-A53
ARM Cortex-
64-bit Core
A53 64b Cores
A53 ARMCores
64b Cortex-
A53 64b Cores
ARM Cortex-
32 KB
32 KB
32 KB
D-Cache
32 KB
32 KB
A53 64b32 KB
Cores
I-Cache
KB
32 KB
32
I-Cache
D-Cache
I-Cache
D-Cache
I-Cache
D-Cache
1 MB L2 - Cache
32-bit
DDR3L/4
Memory Controller
Secure Boot
Trust Zone
Power Management
IFC, QuadSPI, SPI
SD/SDIO/eMMC
DMA
2x DUART
4x I2C, GPIO
8x FlexTimer
3x USB3.0 w/PHY
6x LPUART
DPAA Hardware
4-Lane 10 GHz SerDes
Buffer
Manager
1G
1G
1G
1G
1G
1/2.5G
Security
Engine
(SEC)
CCI-400™ Coherency Fabric
SMMUs
Real Time Debug
Queue
Manager
Frame Manager
PCIe 2.0
PCIe 2.0
PCIe 2.0
SATA 3.0
uQE
Parse, classify,
distribute
Watchpoint
Cross
Trigger
Perf
Monitor
Trace
1/2.5/10G
Core Complex
Accelerators and Memory Control
Basic Peripherals, Interconnect and Debug
Networking Elements
Figure 2. LS1023A Block Diagram
2 Pin assignments
This section describes the ball map diagram and pin list table for both 21x21 and 23x23
packages of LS1043A.
2.1 621 ball layout diagrams
This figure shows the complete view of the LS1043A ball map diagram for the 21x21
package.
Figure 4, Figure 5, Figure 6,
and
Figure 7
show quadrant views.
QorIQ LS1043A, LS1023A Data Sheet, Rev. 1, 06/2016
4
NXP Semiconductors
Pin assignments
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
1
2
3
4
5
6
IFC
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
A
B
C
D
E
SEE DETAIL A
SEE DETAIL B
F
G
H
J
K
L
M
N
P
R
T
U
SEE DETAIL C
SEE DETAIL D
V
W
Y
AA
AB
AC
AD
AE
7
8
9
10
11
12
13
14
15
eSPI
16
17
18
19
20
21
22
23
24
25
DDR Interface 1
DUART
eSDHC
Interrupts
Battery Backed Trust
Trust
System Control
ASLEEP
SYSCLK
DDR Clocking
RTC
Debug
DFT
JTAG
Analog Signals
Serdes 1
USB3 PHY 1
USB3 PHY 2
USB PHY 3
Ethernet MI 1
Ethernet MI 2
Ethernet Cont. 1
Ethernet Cont. 2
I2C
USB
TA_BB_RTC
DIFF_SYSCLK
Power
Ground
No Connects
Figure 3. Complete BGA Map for the LS1043A
QorIQ LS1043A, LS1023A Data Sheet, Rev. 1, 06/2016
NXP Semiconductors
5
嵌入式系统
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
