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74AVCH8T245
8-bit dual supply translating transceiver with configurable
voltage translation; 3-state
Rev. 5 — 27 December 2012
Product data sheet
1. General description
The 74AVCH8T245 is an 8-bit, dual supply transceiver that enables bidirectional level
translation. It features two 8-bit input-output ports (An and Bn), a direction control input
(DIR), a output enable input (OE) and dual supply pins (V
CC(A)
and V
CC(B)
). Both V
CC(A)
and V
CC(B)
can be supplied at any voltage between 0.8 V and 3.6 V making the device
suitable for translating between any of the low voltage nodes (0.8 V, 1.2 V, 1.5 V, 1.8 V,
2.5 V and 3.3 V). Pins An, OE and DIR are referenced to V
CC(A)
and pins Bn are
referenced to V
CC(B)
. A HIGH on DIR allows transmission from An to Bn and a LOW on
DIR allows transmission from Bn to An. The output enable input (OE) can be used to
disable the outputs so the buses are effectively isolated.
The device is fully specified for partial power-down applications using I
OFF
. The I
OFF
circuitry disables the output, preventing any damaging backflow current through the
device when it is powered down. In suspend mode when either V
CC(A)
or V
CC(B)
are at
GND level, both An and Bn outputs are in the high-impedance OFF-state. The bus-hold
circuitry on the powered-up side always stays active.
The 74AVCH8T245 has active bus hold circuitry which is provided to hold unused or
floating data inputs at a valid logic level. This feature eliminates the need for external
pull-up or pull-down resistors.
2. Features and benefits
Wide supply voltage range:
V
CC(A)
: 0.8 V to 3.6 V
V
CC(B)
: 0.8 V to 3.6 V
Complies with JEDEC standards:
JESD8-12 (0.8 V to 1.3 V)
JESD8-11 (0.9 V to 1.65 V)
JESD8-7 (1.2 V to 1.95 V)
JESD8-5 (1.8 V to 2.7 V)
JESD8-B (2.7 V to 3.6 V)
ESD protection:
HBM JESD22-A114E Class 3B exceeds 8000 V
MM JESD22-A115-A exceeds 200 V
CDM JESD22-C101C exceeds 1000 V
Maximum data rates:
380 Mbit/s ( 1.8 V to 3.3 V translation)
260 Mbit/s ( 1.1 V to 3.3 V translation)
NXP Semiconductors
74AVCH8T245
8-bit dual supply translating transceiver; 3-state
260 Mbit/s ( 1.1 V to 2.5 V translation)
210 Mbit/s ( 1.1 V to 1.8 V translation)
150 Mbit/s ( 1.1 V to 1.5 V translation)
100 Mbit/s ( 1.1 V to 1.2 V translation)
Suspend mode
Bus hold on data inputs
Latch-up performance exceeds 100 mA per JESD 78 Class II
Inputs accept voltages up to 3.6 V
I
OFF
circuitry provides partial Power-down mode operation
Multiple package options
Specified from
40 C
to +85
C
and
40 C
to +125
C
3. Ordering information
Table 1.
Ordering information
Package
Temperature range Name
74AVCH8T245PW
40 C
to +125
C
74AVCH8T245BQ
40 C
to +125
C
TSSOP24
Description
plastic thin shrink small outline package; 24 leads;
body width 4.4 mm
Version
SOT355-1
SOT815-1
Type number
DHVQFN24 plastic dual in-line compatible thermal enhanced very
thin quad flat package; no leads; 24 terminals;
body 3.5
5.5
0.85 mm
4. Functional diagram
B1
21
V
CC(A)
V
CC(B)
B2
20
B3
19
B4
18
B5
17
B6
16
B7
15
B8
14
OE
22
DIR
2
3
A1
4
A2
5
A3
6
A4
7
A5
8
A6
9
A7
10
A8
001aai472
Fig 1.
Logic symbol
74AVCH8T245
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 5 — 27 December 2012
2 of 25
NXP Semiconductors
74AVCH8T245
8-bit dual supply translating transceiver; 3-state
DIR
OE
A1
B1
V
CC(A)
V
CC(B)
to other seven channels
001aai473
Fig 2.
Logic diagram (one channel)
5. Pinning information
5.1 Pinning
74AVCH8T245
V
CC(A)
terminal 1
index area
24 V
CC(B)
23 V
CC(B)
22 OE
21 B1
20 B2
19 B3
18 B4
17 B5
16 B6
GND
(1)
GND 12
GND 13
15 B7
14 B8
74AVCH8T245
DIR
V
CC(A)
DIR
A1
A2
A3
A4
A5
A6
A7
1
2
3
4
5
6
7
8
9
24 V
CC(B)
23 V
CC(B)
22 OE
21 B1
20 B2
19 B3
18 B4
17 B5
16 B6
15 B7
14 B8
13 GND
001aai487
2
3
4
5
6
7
8
9
A1
A2
A3
A4
A5
A6
A7
A8 10
GND 11
A8 10
GND 11
GND 12
1
001aai488
Transparent top view
(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to GND.
Fig 3. Pin configuration TSSOP24
Fig 4. Pin configuration DHVQFN24
74AVCH8T245
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 5 — 27 December 2012
3 of 25
NXP Semiconductors
74AVCH8T245
8-bit dual supply translating transceiver; 3-state
5.2 Pin description
Table 2.
Symbol
V
CC(A)
DIR
A1 to A8
GND
[1]
GND
[1]
GND
[1]
B1 to B8
OE
V
CC(B)
V
CC(B)
[1]
Pin description
Pin
1
2
3, 4, 5, 6, 7, 8, 9, 10
11
12
13
22
23
24
Description
supply voltage A (An, OE and DIR inputs are referenced to V
CC(A)
)
direction control
data input or output
ground (0 V)
ground (0 V)
ground (0 V)
output enable input (active LOW)
supply voltage B (Bn inputs are referenced to V
CC(B)
)
supply voltage B (Bn inputs are referenced to V
CC(B)
)
21, 20, 19, 18, 17, 16, 15, 14 data input or output
All GND pins must be connected to ground (0 V).
6. Functional description
Table 3.
Function table
[1]
Input
OE
[2]
L
L
H
X
DIR
[2]
L
H
X
X
Input/output
[3]
An
[2]
An = Bn
input
Z
Z
Bn
input
Bn = An
Z
Z
Supply voltage
V
CC(A)
, V
CC(B)
0.8 V to 3.6 V
0.8 V to 3.6 V
0.8 V to 3.6 V
GND
[3]
[1]
[2]
[3]
H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state.
The An, DIR and OE input circuit is referenced to V
CC(A)
; The Bn input circuit is referenced to V
CC(B)
.
If at least one of V
CC(A)
or V
CC(B)
is at GND level, the device goes into suspend mode.
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC(A)
V
CC(B)
I
IK
V
I
I
OK
V
O
I
O
I
CC
74AVCH8T245
Parameter
supply voltage A
supply voltage B
input clamping current
input voltage
output clamping current
output voltage
output current
supply current
Conditions
Min
0.5
0.5
Max
+4.6
+4.6
-
+4.6
-
V
CCO
+ 0.5
+4.6
50
100
Unit
V
V
mA
V
mA
V
V
mA
mA
V
I
< 0 V
[1]
50
0.5
50
[1][2][3]
[1]
V
O
< 0 V
Active mode
Suspend or 3-state mode
V
O
= 0 V to V
CC
per V
CC(A)
or V
CC(B)
pin
All information provided in this document is subject to legal disclaimers.
0.5
0.5
-
-
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 5 — 27 December 2012
4 of 25
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