74HC00-Q100; 74HCT00-Q100
Quad 2-input NAND gate
Rev. 3 — 19 March 2020
Product data sheet
1. General description
The 74HC00-Q100; 74HCT00-Q100 is a quad 2-input NAND gate. Inputs include clamp diodes.
This enables the use of current limiting resistors to interface inputs to voltages in excess of V
CC
.
This product has been qualified to the Automotive Electronics Council (AEC) standard Q100
(Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
•
•
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
•
Specified from -40 °C to +85 °C and from -40 °C to +125 °C
Input levels:
•
For 74HC00-Q100: CMOS level
•
For 74HCT00-Q100: TTL level
Complies with JEDEC standard no. 7A
ESD protection:
•
MIL-STD-883, method 3015 exceeds 2000 V
•
HBM JESD22-A114F exceeds 2000 V
•
MM JESD22-A115-A exceeds 200 V (C = 200 pf, R = 0 Ω)
Multiple package options
DHVQFN package with Side-Wettable Flanks enabling Automatic Optical Inspection (AOI) of
solder joints
•
•
•
•
3. Ordering information
Table 1. Ordering information
Type number
Package
Temperature range
74HC00D-Q100
74HCT00D-Q100
74HC00PW-Q100
74HCT00PW-Q100
74HC00BQ-Q100
74HCT00BQ-Q100
-40 °C to +125 °C
DHVQFN14
-40 °C to +125 °C
TSSOP14
-40 °C to +125 °C
Name
SO14
Description
plastic small outline package; 14 leads;
body width 3.9 mm
Version
SOT108-1
plastic thin shrink small outline package; 14 leads; SOT402-1
body width 4.4 mm
plastic dual in-line compatible thermal
enhanced very thin quad flat package; no leads;
14 terminals; body 2.5 × 3 × 0.85 mm
SOT762-1
Nexperia
74HC00-Q100; 74HCT00-Q100
Quad 2-input NAND gate
4. Functional diagram
1 1A
2 1B
4 2A
5 2B
9 3A
10 3B
12 4A
13 4B
1
1Y 3
2Y 6
3Y 8
4Y 11
mna212
2
4
5
9
10
12
13
&
3
&
6
&
8
A
Y
B
mna211
&
mna246
11
Fig. 1.
Logic symbol
Fig. 2.
IEC logic symbol
Fig. 3.
Logic diagram (one gate)
5. Pinning information
5.1. Pinning
74HC00-Q100
74HCT00-Q100
terminal 1
index area
14 V
CC
1A
2
3
4
5
6
7
GND
3Y
8
GND
(1)
1
74HC00-Q100
74HCT00-Q100
1A
1B
1Y
2A
2B
2Y
GND
1
2
3
4
5
6
7
aaa-003147
1B
1Y
2A
14 V
CC
13 4B
12 4A
11 4Y
10 3B
9
8
3A
3Y
13 4B
12 4A
11 4Y
10 3B
9
3A
2B
2Y
aaa-003148
Transparent top view
Fig. 4.
Pin configuration SOT108-1 (SO14) and
SOT402-1 (TSSOP14)
(1) This is not a ground pin. There is no electrical or
mechanical requirement to solder the pad. In case
soldered, the solder land should remain floating or
connected to GND.
Fig. 5.
Pin configuration SOT762-1 (DHVQFN14)
5.2. Pin description
Table 2. Pin description
Symbol
1A to 4A
1B to 4B
1Y to 4Y
GND
V
CC
Pin
1, 4, 9, 12
2, 5, 10, 13
3, 6, 8, 11
7
14
Description
data input
data input
data output
ground (0 V)
supply voltage
74HC_HCT00_Q100
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2020. All rights reserved
Product data sheet
Rev. 3 — 19 March 2020
2 / 12
Nexperia
74HC00-Q100; 74HCT00-Q100
Quad 2-input NAND gate
6. Functional description
Table 3. Function table
H = HIGH voltage level; L = LOW voltage level; X = don’t care.
Input
nA
L
X
H
nB
X
L
H
Output
nY
H
H
L
7. Limiting values
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
V
CC
I
IK
I
OK
I
O
I
CC
I
GND
T
stg
P
tot
[1]
[2]
Conditions
V
I
< -0.5 V or V
I
> V
CC
+ 0.5 V
V
O
< -0.5 V or V
O
> V
CC
+ 0.5 V
-0.5 V < V
O
< V
CC
+ 0.5 V
[1]
[1]
Min
-0.5
-
-
-
-
-50
-65
[2]
-
Max
+7
±20
±20
±25
50
-
+150
500
Unit
V
mA
mA
mA
mA
mA
°C
mW
supply voltage
input clamping current
output clamping current
output current
supply current
ground current
storage temperature
total power dissipation
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
For SOT108-1 (SO14) package: P
tot
derates linearly with 10.1 mW/K above 100 °C.
For SOT402-1 (TSSOP14) package: P
tot
derates linearly with 7.3 mW/K above 81 °C.
For SOT762-1 (DHVQFN14) package: P
tot
derates linearly with 9.6 mW/K above 98 °C.
8. Recommended operating conditions
Table 5. Recommended operating conditions
Voltages are referenced to GND (ground = 0 V)
Symbol Parameter
V
CC
V
I
V
O
T
amb
Δt/ΔV
supply voltage
input voltage
output voltage
ambient temperature
input transition rise and fall rate
V
CC
= 2.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
Conditions
2.0
0
0
-40
-
-
-
74HC00-Q100
Min
Typ
5.0
-
-
+25
-
1.67
-
Max
6.0
V
CC
V
CC
+125
625
139
83
74HCT00-Q100
Min
4.5
0
0
-40
-
-
-
Typ
5.0
-
-
+25
-
1.67
-
Max
5.5
V
CC
V
CC
+125
-
139
-
V
V
V
°C
ns/V
ns/V
ns/V
Unit
74HC_HCT00_Q100
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2020. All rights reserved
Product data sheet
Rev. 3 — 19 March 2020
3 / 12
Nexperia
74HC00-Q100; 74HCT00-Q100
Quad 2-input NAND gate
9. Static characteristics
Table 6. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
74HC00-Q100
V
IH
HIGH-level
input voltage
V
CC
= 2.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
V
IL
LOW-level
input voltage
V
CC
= 2.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
V
OH
HIGH-level
output voltage
V
I
= V
IH
or V
IL
I
O
= -20 μA; V
CC
= 2.0 V
I
O
= -20 μA; V
CC
= 4.5 V
I
O
= -20 μA; V
CC
= 6.0 V
I
O
= -4.0 mA; V
CC
= 4.5 V
I
O
= -5.2 mA; V
CC
= 6.0 V
V
OL
LOW-level
output voltage
V
I
= V
IH
or V
IL
I
O
= 20 μA; V
CC
= 2.0 V
I
O
= 20 μA; V
CC
= 4.5 V
I
O
= 20 μA; V
CC
= 6.0 V
I
O
= 4.0 mA; V
CC
= 4.5 V
I
O
= 5.2 mA; V
CC
= 6.0 V
I
I
I
CC
C
I
input leakage
current
supply current
input
capacitance
HIGH-level
input voltage
LOW-level
input voltage
HIGH-level
output voltage
V
CC
= 4.5 V to 5.5 V
V
CC
= 4.5 V to 5.5 V
V
I
= V
IH
or V
IL
; V
CC
= 4.5 V
I
O
= -20 μA
I
O
= -4.0 mA
V
OL
LOW-level
output voltage
V
I
= V
IH
or V
IL
; V
CC
= 4.5 V
I
O
= 20 μA; V
CC
= 4.5 V
I
O
= 5.2 mA; V
CC
= 6.0 V
-
-
0
0.15
-
-
-
-
0.1
0.33
-
-
0.1
0.4
V
V
-
-
4.5
4.32
-
-
4.4
3.84
-
-
4.4
3.7
-
-
V
V
V
I
= V
CC
or GND; V
CC
= 6.0 V
V
I
= V
CC
or GND; I
O
= 0 A;
V
CC
= 6.0 V
-
-
-
-
-
-
-
-
0
0
0
0.15
0.16
-
-
3.5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.1
0.1
0.1
0.33
0.33
±1
20
-
-
-
-
-
-
-
-
-
0.1
0.1
0.1
0.4
0.4
±1
40
-
V
V
V
V
V
μA
μA
pF
-
-
-
-
-
2.0
4.5
6.0
4.32
5.81
-
-
-
-
-
1.9
4.4
5.9
3.84
5.34
-
-
-
-
-
1.9
4.4
5.9
3.7
5.2
-
-
-
-
-
V
V
V
V
V
-
-
-
-
-
-
1.2
2.4
3.2
0.8
2.1
2.8
-
-
-
-
-
-
1.5
3.15
4.2
-
-
-
-
-
-
0.5
1.35
1.8
1.5
3.15
4.2
-
-
-
-
-
-
0.5
1.35
1.8
V
V
V
V
V
V
25 °C
Typ
Max
-40 °C to
+85 °C
Min
Max
-40 °C to
+125 °C
Min
Max
Unit
74HCT00-Q100
V
IH
V
IL
V
OH
-
-
1.6
1.2
-
-
2.0
-
-
0.8
2.0
-
-
0.8
V
V
74HC_HCT00_Q100
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2020. All rights reserved
Product data sheet
Rev. 3 — 19 March 2020
4 / 12
Nexperia
74HC00-Q100; 74HCT00-Q100
Quad 2-input NAND gate
Conditions
Min
25 °C
Typ
-
-
150
Max
-
-
-
-40 °C to
+85 °C
Min
-
-
-
Max
±1
20
675
-40 °C to
+125 °C
Min
-
-
-
Max
±1
40
735
μA
μA
μA
Unit
Symbol Parameter
I
I
I
CC
ΔI
CC
input leakage
current
supply current
additional
supply current
V
I
= V
CC
or GND; V
CC
= 6.0 V
V
I
= V
CC
or GND; I
O
= 0 A;
V
CC
= 6.0 V
per input pin;
V
I
= V
CC
- 2.1 V; I
O
= 0 A;
other inputs at V
CC
or GND;
V
CC
= 4.5 V to 5.5 V
-
-
-
C
I
input
capacitance
-
3.5
-
-
-
-
-
pF
10. Dynamic characteristics
Table 7. Dynamic characteristics
GND = 0 V; C
L
= 50 pF; for test circuit see
Fig. 7.
Symbol Parameter
Conditions
Min
74HC00-Q100
t
pd
propagation delay nA, nB to nY; see
Fig. 6
V
CC
= 2.0 V
V
CC
= 4.5 V
V
CC
= 5.0 V; C
L
= 15 pF
V
CC
= 6.0 V
t
t
transition time
see
Fig. 6
V
CC
= 2.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
C
PD
power dissipation per package;
capacitance
V
I
= GND to V
CC
propagation delay nA, nB to nY; see
Fig. 6
V
CC
= 4.5 V
V
CC
= 5.0 V; C
L
= 15 pF
t
t
C
PD
[1]
[2]
[3]
25 °C
Typ
Max
-40 °C to
+85 °C
Min
Max
-40 °C to
+125 °C
Min
Max
Unit
[1]
-
-
-
-
[2]
-
-
-
[3]
-
19
7
6
22
-
-
-
-
-
-
-
-
95
19
16
-
-
-
-
-
110
22
19
-
ns
ns
ns
pF
25
9
7
7
-
-
-
-
-
-
-
-
115
23
-
20
-
-
-
-
135
27
-
23
ns
ns
ns
ns
74HCT00-Q100
t
pd
[1]
-
-
[2]
[3]
-
-
12
10
-
22
-
-
-
-
-
-
-
-
24
-
29
-
-
-
-
-
29
-
22
-
ns
ns
ns
pF
transition time
V
CC
= 4.5 V; see
Fig. 6
power dissipation per package;
capacitance
V
I
= GND to V
CC
- 1.5 V
t
pd
is the same as t
PHL
and t
PLH
.
t
t
is the same as t
THL
and t
TLH
.
C
PD
is used to determine the dynamic power dissipation (P
D
in μW):
2
2
P
D
= C
PD
× V
CC
× f
i
× N + Σ (C
L
× V
CC
× f
o
) where:
f
i
= input frequency in MHz; f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in V;
N = number of inputs switching;
2
Σ (C
L
× V
CC
× f
o
) = sum of outputs.
74HC_HCT00_Q100
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2020. All rights reserved
Product data sheet
Rev. 3 — 19 March 2020
5 / 12
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