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CY7C243-20JC

产品描述OTP ROM, 4KX8, 20ns, CMOS, PQCC28, PLASTIC, LCC-28
产品类别存储    存储   
文件大小290KB,共11页
制造商Cypress(赛普拉斯)
下载文档 详细参数 全文预览

CY7C243-20JC概述

OTP ROM, 4KX8, 20ns, CMOS, PQCC28, PLASTIC, LCC-28

CY7C243-20JC规格参数

参数名称属性值
是否Rohs认证不符合
厂商名称Cypress(赛普拉斯)
零件包装代码QLCC
包装说明PLASTIC, LCC-28
针数28
Reach Compliance Codenot_compliant
ECCN代码EAR99
最长访问时间20 ns
I/O 类型COMMON
JESD-30 代码S-PQCC-J28
JESD-609代码e0
内存密度32768 bit
内存集成电路类型OTP ROM
内存宽度8
功能数量1
端子数量28
字数4096 words
字数代码4000
工作模式ASYNCHRONOUS
最高工作温度70 °C
最低工作温度
组织4KX8
输出特性3-STATE
封装主体材料PLASTIC/EPOXY
封装代码QCCJ
封装等效代码LDCC28,.5SQ
封装形状SQUARE
封装形式CHIP CARRIER
并行/串行PARALLEL
峰值回流温度(摄氏度)NOT SPECIFIED
电源5 V
认证状态Not Qualified
最大压摆率0.1 mA
最大供电电压 (Vsup)5.5 V
最小供电电压 (Vsup)4.5 V
标称供电电压 (Vsup)5 V
表面贴装YES
技术CMOS
温度等级COMMERCIAL
端子面层Tin/Lead (Sn/Pb)
端子形式J BEND
端子节距1.27 mm
端子位置QUAD
处于峰值回流温度下的最长时间NOT SPECIFIED
Base Number Matches1

文档预览

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1CY 7C24 4
CY7C243
CY7C244
4Kx8 Reprogrammable PROM
Features
CMOS for optimum speed/power
Windowed for reprogrammability
High speed
Functional Description
The CY7C243 and CY7C244 are high-performance 4K x 8
CMOS PROMs. The CY7C243 and CY7C244 are packaged in
300-mil-wide and 600-mil-wide packages respectively. The re-
programmable packages are equipped with an erasure win-
dow. When exposed to UV light, these PROMs are erased and
can then be reprogrammed. The memory cells utilize proven
EPROM floating-gate technology and byte-wide intelligent pro-
gramming algorithms.
The CY7C243 and CY7C244 are plug-in replacements for bi-
polar devices and offer the advantages of lower power, supe-
rior performance and programming yield. The EPROM cell re-
quires only 12.5V for the supervoltage and low current
requirements allow for gang programming. The EPROM cells
allow for each memory location to be tested 100%, as each
cell is programmed, erased, and repeatedly exercised prior to
encapsulation. Each PROM is also tested for AC performance
to guarantee that after customer programming the product will
meet DC and AC specification limits.
Read is accomplished by placing an active LOW signal on CS
1
and an active HIGH on CS
2
. The contents of the memory lo-
cation addressed by the address line (A
0
A
11
) will become
available on the output lines (O
0
O
7
).
20 ns (commercial)
25 ns (military)
Low power
550 mW (commercial)
660 mW (military)
EPROM technology 100% programmable
300-mil or 600-mil packaging available
5V
±
10% V
CC
, commercial and military
Capable of withstanding greater than 2001V static
discharge
TTL-compatible I/O
Direct replacement for bipolar PROMs
Logic Block Diagram
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
A
10
A
11
COLUMN
ADDRESS
O
3
ADDRESS
DECODER
O
4
O
5
ROW
ADDRESS
PROGRAM-
MABLE
ARRAY
COLUMN
MULTI-
PLEXER
O
7
Pin Configurations
DIP/Flatboat
Top View
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
O
0
O
1
O
2
GND
1
24
2
23
3
22
4
21
5
20
6
19
18
7
17
8
9 7C243 16
10
15
11 7C244 14
12
13
V
CC
A
8
A
9
A
10
CS
1
A
11
CS
2
O
7
O
6
O
5
O
4
O
3
C243-2
O
6
O
2
LCC/PLCC (Opaque Only)
Top View
4 3 2 1 2827 26
25
5
24
6
23
7
7C243
22
8
21
9
20
10
19
11
12 1314151617 18
O
1
A
4
A
3
A
2
A
1
A
0
NC
O
0
O
0
CS
1
CS
2
C243-1
A
10
CS
1
A
11
CS
2
NC
O
7
O
6
C243-3
Selection Guide
7C243-20
7C244-20
20
100
7C243-25
7C244-25
25
100
120
7C243-35
7C244-35
35
80
100
7C243-45
7C244-45
45
80
100
7C243-55
7C244-55
55
80
100
Maximum Access Time (ns)
Maximum Operating
Commercial
Current (mA)
Military
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134 •
408-943-2600
May 1994 – Revised August 1994

 
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