SwitchStar
TM
ATM Cell Based
1.2Gbps non-blocking
Integrated Switch Controller
Features
Single chip controller for IDT77V400 Switching Memory
One IDT77V500 and one IDT77V400 form the core required
for a 1.2Gbps 8 x 8 port non-blocking switch
x
Supports up to 8192 Virtual Connections (VCs)
x
Per VC queuing for fairness, with four priorities per VC
available for each output port of the switch
x
Capable of supporting CBR, VBR, UBR, and ABR (EFCI)
service classes
x
Low power dissipation
– 430mW (typ.)
x
Optional header modification operation
x
Multicasting and Broadcasting capability
x
Provides congestion management support through EFCI,
CLP, and EPD functionality
x
System clock cycle times as fast as 25ns (40MHz)
x
Option available for resolving contention issues between
multiple IDT77V500 configurations
x
x
x
IDT77V500
x
x
x
One IDT77V500 can manage up to eight IDT77V400's
without derating for larger switch configurations
Industrial temperature range (-40° C to +85° C) is available
Single +3.3V ± 300mV power supply
Available in a 100-pin Thin Plastic Quad Flat Pack (TQFP)
and 144-ball BGA
Description
The IDT77V500 ATM Cell Based Switch Controller, when paired with
the IDT77V400 Switching Memory, forms the core control logic and
switch fabric for a 1.2Gbps non-blocking ATM switch. The IDT77V500
manages all of the switch traffic moving through the IDT77V400,
commanding the storage of incoming ATM cells and interpreting and
modifying the cell header information as necessary for data flow through
the switch. It then uses the header information, including priority indica-
tors, to queue and direct the individual cells for transmission out the
appropriate output port of the IDT77V400.
Typical 8 x 8 Switch Configuration using the IDT77V500 Switch Controller
External Interface
for Global Setup
and Control
8-bit Processor/
/
Call Setup
Manager
or IDT77V550
Data
IDT77V500
Control
Switch
Controller
Data
Control
Port 0
155Mbps
PHY
Port 0
155Mbps
PHY
IDT77V400
Switching
Memory
155Mbps
PHY
Port 7
Port 7
155Mbps
PHY
3607 drw 01
,
SwitchStar and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
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2001 Integrated Device Technology, Inc.
April 11, 2001
DSC 3607/5
IDT77V500
The IDT77V500 utilizes Per Virtual Connection (VC) Queuing to keep
track of each call, and has the capacity to keep track of as many as 8192
individual VC queues. There are four possible priorities available for
each of the assigned outputs of the Switching Memory, and CBR, VBR,
UBR, and ABR-EFCI service classes are supported by the Switch
Controller. Multicasting and broadcasting services are provided,
requiring only the appropriate header information to execute these oper-
ations automatically without requiring multiple Switching Memory
entries.
The IDT77V500 also has a mode for managing and transmitting
packetized data, enabling easy transition between packet oriented
networks such as Ethernet and FDDI and ATM cell oriented networks.
The IDT77V500 has an 8-bit Manager Bus interface, MDATA0-7, to a
Call Setup Manager processor for the configuration activity and call
setup operation. When a Call Setup Cell is received by the IDT77V400,
the cell is directed to a specified output port and the payload processed
by the Call Setup Manager. The new Virtual Connection (VC) is then
established in the Queue Manager of the IDT77V500, with all operations
executed across the 8-bit Manager Bus. Subsequent cells of that partic-
ular VC are then prioritized and directed by the Switch Controller as they
are received by the IDT77V400; no further interaction with the Call
Manager processor is required for ongoing queue and cell management.
The IDT77V500 supports a major subset of the available commands
and configurations of the IDT77V400 Switching Memory. Please refer to
the SwitchStar User Manual for additional feature details and implemen-
tation information.
The IDT77V500 is fully 3.3V LVTTL compatible, and is packaged in
an 100-pin Thin Plastic Quad Flatpack (TQFP) and an 144-ball BGA.
Functional Block Diagram
MD/C
MR/W
MSTRB
MDATA0-7
Call
Setup
Manager
State
Machine
OFRM0-7
CBRCLK2
CBRCLK3
Output
Service
and
Arbitration
SFRM
Queue Manager
2
SCLK
RESETI
Control
Logic
SCLK
1
Reset
1
Output Queues
and
Link Registers
RESETO
2
Switching Memory Interface
32
6
IOD0-31
1
2
CMD0-5
2
3607 drw 02
CRCERR
SCLK and Reset are inputs to all blocks.
Outputs are always enabled (active).
2 of 17
April 11, 2001
IDT77V500
Package Diagrams
All Vcc pins must be connected to power supply. All Vss pins must be connected to ground supply.
Index
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
MDATA
7
MD/C
MR/W
MSTRB
NC
NC
CMD5
CMD4
CMD3
V
SS
V
CC
CMD2
CMD1
CMD0
NC
NC
RESETI
SCLK
RESETO
CBRCLK2
NC
CBRCLK3
NC
SFRM
OFRM7
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
NC
NC
MDATA
6
MDATA
5
MDATA
4
V
SS
V
CC
MDATA
3
MDATA
2
MDATA
1
MDATA
0
V
CC
V
CC
V
CC
CRCERR
IOD
0
IOD
1
IOD
2
IOD
3
V
CC
V
SS
IOD
4
IOD
5
IOD
6
NC
75
74
73
72
71
70
69
68
67
IDT77V500PF
PN100-1
1
100-Pin TQFP
Top View
2
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
NC
NC
IOD
7
IOD
8
IOD
9
IOD
10
IOD
11
V
CC
V
SS
IOD
12
IOD
13
IOD
14
IOD
15
IOD
16
IOD
17
IOD
18
IOD
19
V
CC
V
SS
IOD
20
IOD
21
IOD
22
IOD
23
NC
NC
,
3607 drw 03
1
2
This text
This package code is used to reference the package diagram.
does not indicate orientation of the actual part marking.
NC
NC
OFRM
6
OFRM
5
V
SS
V
CC
OFRM
4
OFRM
3
OFRM
2
OFRM
1
OFRM
0
V
SS
V
SS
V
SS
IOD
31
IOD
30
IOD
29
IOD
28
V
SS
V
CC
IOD
27
IOD
26
IOD
25
IOD
24
NC
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April 11, 2001
IDT77V500
BGA Package Diagram
1
A
B
C
D
E
F
G
H
J
K
L
M
VCC
VSS
NC
NC
NC
NC
VCC
IOD31
IOD29
NC
NC
NC
1
2
NC
OFRM2
NC
NC
NC
NC
VSS
IOD30
NC
IOD26
NC
NC
2
3
OFRM4
OFRM3
NC
NC
NC
VSS
NC
NC
VSS
IOD25
IOD22
IOD23
3
4
OFRM7
NC
OFRM5
OFRM1
NC
VSS
NC
IOD27
IOD24
IOD20
VSS
IOD21
4
5
CBRCLK2
6
SCLK
7
NC
RESETI
NC
NC
8
VCC
VSS
CMD1
CMD0
NC
VCC
VCC
VCC
IOD6
VSS
IOD10
IOD11
8
9
CMD4
CMD5
CMD3
NC
NC
MDATA2
NC
NC
NC
VCC
IOD7
IOD9
9
10
NC
MSTRB
MR/W
NC
MDATA3
MDATA0
NC
NC
IOD0
IOD3
NC
NC
10
11
MDATA7
MD/C
MDATA5
VSS
MDATA1
NC
NC
NC
NC
IOD2
VSS
NC
11
12
NC
MDATA6
NC
MDATA4
NC
NC
NC
NC
IOD1
NC
IOD4
IOD5
12
A
B
C
D
E
F
G
H
J
K
L
M
CBRCLK3 RESETO
SFRM
OFRM6
OFRM0
NC
IOD28
VCC
IOD17
NC
NC
IOD18
5
NC
NC
VCC
NC
IOD19
IOD12
IOD14
IOD15
NC
IOD16
6
NC
CMD2
CRCERR
IOD8
VCC
IOD13
NC
NC
7
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April 11, 2001
IDT77V500
TQFP Pin Description
Pin Number
18
22,20
Symbol
SCLK
CBRCLK3,
CBRCLK2
I
I
Type
Description
System clock: Reference clock input for all synchronous pins of the IDT77V500 Switch Controller. All synchro-
nous signals are referenced to the rising edge of SCLK.
CBR Clocks 3 and 2: External clock signals used when Constant Bit Rate (CBR) Service classes are utilized.
These clock signals correspond to Output Port priorities 3 and 2 respectively and are used to determine the
constant bit rate for the controller. Priority 3 is the highest priority. If CBR mode is not used these pins should
be pulled up to Vcc with a resistor with a recommended value of 5K ohm or less.
Cyclical Redundancy Check Error: Synchronous input on the rising edge of SCLK. CRCERR asserted LOW
by the IDT77V400 Switching Memory during a store operation indicates that a HEC CRC error has occurred in
the cell header.
Manager Control: Selects the data or control registers of the IDT77V500 for the Manager Bus Operation.
MD/C asserted HIGH selects the data registers, and MD/C LOW selects the command/status registers of the
IDT77V500.
Manager Read/Write: MR/W LOW will write the data on the Manager Bus into the registers selected by the
MD/C input. In write mode (MR/W LOW) the data on MDATA0-7 is written synchronously with respect to the
rising edge of MSTRB; in read mode (MR/W HIGH) the data is accessed asynchronously.
Manager Strobe: Input which acts as a clock for the Manager Bus (MDATA0-7). Other Manager Bus inputs are
synchronous to the rising edge of MSTRB during write operations (MR/W LOW) and must meet the specified
Setup and Hold parameters. MSTRB performs an asynchronous Output Enable function when a read opera-
tion (MR/W HIGH) is executed on the Manager Bus. When MSTRB is LOW and MR/W is HIGH (Read Mode)
the Manager Bus is enabled in output mode and the contents of the IDT77V500 registers (determined by the
MD/C input) are available to be read on MDATA0-7.
Reset Input: When asserted HIGH, this signal asynchronously initiates the internal reset sequence of the
IDT77V500.
Reset Output: Asserted HIGH upon initiating the reset of the IDT77V500 (RESETI HIGH). In multiple
IDT77V500 configurations, this output is connected to the RESETI input of the next controller in the chain.
RESETO will remain HIGH until a START command is received from the Call Setup Manager.
Command Bus: Synchronized with SCLK, instructions to be executed by the IDT77V400 Switching memory
are output by the IDT77V500 on this 6-bit bus.
Synchronize Output Frame: Synchronous output used when multiple IDT77V500's contend for a common bus.
The Master IDT77V500 generates this signal which then drives the OFRM0 input of the other IDT77V500s.
Control Data Bus: Synchronous with SCLK and one cycle latent to the Command Bus (CMD0-5). Used for
transfer of the header bytes, configuration register, error and status registers, and the cell memory address
between the IDT77V500 and the IDT77V400 Switching Memory.
Manager Bus: Communications between the Call Setup Manager and the IDT77V500 occur over this 8-bit bi-
directional bus. MD/C, MR/W, and MSTRB determine the mode and data type transferred across the MDATA
bus. Write operations are synchronous with respect to MSTRB, while MDATA behaves asynchronously for
read operations.
Output Frame: Asynchronous input pins used by the IDT77V500 to detect when the next cell can be loaded to
the specified IDT77V400 output port 0 through 7. When in multiple IDT77V500 configurations, the OFRM1-7
are redefined as CBUS1-7 for arbitration. OFRM0 is always an input pin (There is no CBUS0).
Power Supply (+3.3V ±300mV)
Ground
No Connect
86
CRCERR
I
2
MD/C
I
3
MR/W
I
4
MSTRB
I
17
19
RESETI
RESETO
I
O
7-9, 12-14
24
CMD0-5
SFRM
O
O
I/O
40-43, 46-49, 53-56, 59-66, IOD0-31
69-73, 77-79, 82-85
1, 90-93, 96-98
MDATA0-7
I/O
25, 28-29, 32-35, 36
OFRM1-7
OFRM0
VCC
VSS
NC
I/O
11, 31, 45, 58, 68, 81, 87-
89, 94
10, 30, 37-39, 44, 57, 67,
80, 95
5-6, 15-16, 21, 23, 26-27,
50-52, 74-76, 99-100
Power
Power
____
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April 11, 2001
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