74AHC595; 74AHCT595
Rev. 6 — 26 May 2020
8-bit serial-in/serial-out or parallel-out shift register with
output latches
Product data sheet
1. General description
The 74AHC595; 74AHCT595 is an 8-bit serial-in/serial or parallel-out shift register with a storage
register and 3-state outputs. Both the shift and storage register have separate clocks. The device
features a serial input (DS) and a serial output (Q7S) to enable cascading and an asynchronous
reset MR input. A LOW on MR will reset the shift register. Data is shifted on the LOW-to-HIGH
transitions of the SHCP input. The data in the shift register is transferred to the storage register
on a LOW-to-HIGH transition of the STCP input. If both clocks are connected together, the shift
register will always be one clock pulse ahead of the storage register. Data in the storage register
appears at the output whenever the output enable input (OE) is LOW. A HIGH on OE causes
the outputs to assume a high-impedance OFF-state. Operation of the OE input does not affect
the state of the registers. The 74AHCT595 features TTL compatible inputs. Both 74AHC595
and 74AHCT595 inputs are overvoltage tolerant. This feature allows the use of these devices as
translators in mixed voltage environments.
2. Features and benefits
•
•
•
•
•
•
•
Wide supply voltage range from 2.0 V to 5.5 V
Balanced propagation delays
All inputs have Schmitt-trigger action
Overvoltage tolerant inputs to 5.5 V
High noise immunity
CMOS low power dissipation
Input levels:
•
The 74AHC595 operates with CMOS input levels
•
The 74AHCT595 operates with TTL input levels
ESD protection:
•
HBM JESD22-A114F exceeds 2000 V
•
MM JESD22-A115-A exceeds 200 V
•
CDM JESD22-C101E exceeds 1000 V
Latch-up performance exceeds 100 mA per JESD 78 Class II Level A
Multiple package options
Specified from -40 °C to +85 °C and from -40 °C to +125 °C
•
•
•
•
3. Applications
•
•
Serial-to-parallel data conversion
Remote control holding register
Nexperia
74AHC595; 74AHCT595
8-bit serial-in/serial-out or parallel-out shift register with output latches
4. Ordering information
Table 1. Ordering information
Type number
Package
Temperature range
74AHC595D
74AHCT595D
74AHC595PW
74AHCT595PW
74AHC595BQ
74AHCT595BQ
-40 °C to +125 °C
DHVQFN16
-40 °C to +125 °C
TSSOP16
-40 °C to +125 °C
Name
SO16
Description
plastic small outline package; 16 leads;
body width 3.9 mm
plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
Version
SOT109-1
SOT403-1
plastic dual in-line compatible thermal enhanced
SOT763-1
very thin quad flat package; no leads; 16 terminals;
body 2.5 × 3.5 × 0.85 mm
5. Functional diagram
14 DS
11 SHCP
10 MR
8-STAGE SHIFT REGISTER
Q7S
12 STCP
8-BIT STORAGE REGISTER
9
13 OE
3-STATE OUTPUTS
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
15 1
2
3
4
5
6
7
mna554
Fig. 1.
Functional diagram
13
11
12
Q7S
Q0
Q1
14
Q2
DS
Q3
Q4
Q5
Q6
Q7
MR
10
OE
13
mna552
12
10
9
15
1
2
3
4
5
6
7
EN3
C2
R
C1/
1D
2D
3
15
1
2
3
4
5
6
7
9
mna553
SHCP STCP
11
14
SRG8
Fig. 2.
Logic symbol
Fig. 3.
IEC logic symbol
74AHC_AHCT595
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2020. All rights reserved
Product data sheet
Rev. 6 — 26 May 2020
2 / 19
Nexperia
74AHC595; 74AHCT595
8-bit serial-in/serial-out or parallel-out shift register with output latches
STAGE 0
DS
D
FF0
CP
SHCP
MR
R
Q
D
STAGES 1 TO 6
Q
STAGE 7
D
FF7
CP
R
Q
Q7S
D
CP
STCP
OE
Q
D
CP
Q
LATCH
LATCH
Q0
Q1 Q2 Q3 Q4 Q5 Q6
Q7
mna555
Fig. 4.
Logic diagram
6. Pinning information
6.1. Pinning
74AHC595
74AHCT595
terminal 1
index area
Q2
2
3
4
5
6
7
8
GND
Q7S
9
GND
(1)
16 V
CC
15 Q0
14 DS
13 OE
12 STCP
11 SHCP
10 MR
Q1
1
74AHC595
74AHCT595
Q1
Q2
Q3
Q4
Q5
Q6
Q7
GND
1
2
3
4
5
6
7
8
001aae538
Q3
Q4
16 V
CC
15 Q0
14 DS
13 OE
12 STCP
11 SHCP
10 MR
9
Q7S
Q5
Q6
Q7
001aae483
Transparent top view
Fig. 5.
Pin configuration SOT109-1 (SO16) and
SOT403-1 (TSSOP16)
(1) This is not a ground pin. There is no electrical or
mechanical requirement to solder the pad. In case
soldered, the solder land should remain floating or
connected to GND.
Fig. 6.
Pin configuration SOT763-1 (DHVQFN16)
74AHC_AHCT595
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2020. All rights reserved
Product data sheet
Rev. 6 — 26 May 2020
3 / 19
Nexperia
74AHC595; 74AHCT595
8-bit serial-in/serial-out or parallel-out shift register with output latches
6.2. Pin description
Table 2. Pin description
Symbol
Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7
GND
Q7S
MR
SHCP
STCP
OE
DS
V
CC
Pin
15, 1, 2, 3, 4, 5, 6, 7
8
9
10
11
12
13
14
16
Description
parallel data output
ground (0 V)
serial data output
master reset (active LOW)
shift register clock input
storage register clock input
output enable input (active LOW)
serial data input
supply voltage
7. Functional description
Table 3. Function table
H = HIGH voltage state;
L = LOW voltage state;
↑ = LOW-to-HIGH transition;
X = don’t care;
NC = no change;
Z = high-impedance OFF-state.
Control
SHCP STCP
X
X
X
↑
X
↑
X
X
OE
L
L
H
L
MR
L
L
L
H
Input
DS
X
X
X
H
Output
Q7S
L
L
L
Q6S
Qn
NC
L
Z
NC
a LOW-level on MR only affects the shift registers
empty shift register loaded into storage register
shift register clear; parallel outputs in high-impedance OFF-state
logic HIGH-level shifted into shift register stage 0. Contents of
all shift register stages shifted through, e.g. previous state of
stage 6 (internal Q6S) appears on the serial output (Q7S).
contents of shift register stages (internal QnS) are transferred to
the storage register and parallel output stages
contents of shift register shifted through; previous contents of the
shift register is transferred to the storage register and the parallel
output stages
Function
X
↑
↑
↑
L
L
H
H
X
X
NC
Q6S
QnS
QnS
74AHC_AHCT595
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2020. All rights reserved
Product data sheet
Rev. 6 — 26 May 2020
4 / 19
Nexperia
74AHC595; 74AHCT595
8-bit serial-in/serial-out or parallel-out shift register with output latches
SHCP
DS
STCP
MR
OE
Q0
Q1
Z-state
Z-state
Q6
Q7
Q7S
Z-state
Z-state
mna556
Fig. 7.
Timing diagram
8. Limiting values
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
V
CC
V
I
I
IK
I
OK
I
O
I
CC
I
GND
T
stg
P
tot
[1]
[2]
Conditions
Min
-0.5
-0.5
Max
+7.0
+7.0
-
+20
+25
+75
-
+150
500
Unit
V
V
mA
mA
mA
mA
mA
°C
mW
supply voltage
input voltage
input clamping current
output clamping current
output current
supply current
ground current
storage temperature
total power dissipation
T
amb
= -40 °C to +125 °C
[2]
V
I
< -0.5 V
V
O
< -0.5 V or V
O
> V
CC
+ 0.5 V
V
O
= -0.5 V to (V
CC
+ 0.5 V)
[1]
[1]
-20
-20
-25
-
-75
-65
-
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
For SOT109-1 (SO16) package: P
tot
derates linearly with 12.4 mW/K above 110 °C.
For SOT403-1 (TSSOP16) package: P
tot
derates linearly with 8.5 mW/K above 91 °C.
For SOT763-1 (DHVQFN16) package: P
tot
derates linearly with 11.2 mW/K above 106 °C.
74AHC_AHCT595
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2020. All rights reserved
Product data sheet
Rev. 6 — 26 May 2020
5 / 19
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