INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
•
The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
•
The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
•
The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT164
8-bit serial-in/parallel-out shift
register
Product specification
File under Integrated Circuits, IC06
December 1990
Philips Semiconductors
Product specification
8-bit serial-in/parallel-out shift register
FEATURES
•
Gated serial data inputs
•
Asynchronous master reset
•
Output capability: standard
•
I
CC
category: MSI
GENERAL DESCRIPTION
The 74HC/HCT164 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT164 are 8-bit edge-triggered shift registers
with serial data entry and an output from each of the eight
stages.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°C;
t
r
= t
f
= 6 ns
74HC/HCT164
Data is entered serially through one of two inputs (D
sa
or
D
sb
); either input can be used as an active HIGH enable for
data entry through the other input.
Both inputs must be connected together or an unused
input must be tied HIGH.
Data shifts one place to the right on each LOW-to-HIGH
transition of the clock (CP) input and enters into Q
0
, which
is the logical AND of the two data inputs (D
sa
,D
sb
) that
existed one set-up time prior to the rising clock edge.
A LOW level on the master reset (MR) input overrides all
other inputs and clears the register asynchronously,
forcing all outputs LOW.
TYPICAL
SYMBOL
t
PHL
/ t
PLH
PARAMETER
propagation delay
CP to Q
n
MR to Q
n
maximum clock frequency
input capacitance
power dissipation capacitance per
package
notes 1 and 2
CONDITIONS
HC
C
L
= 15 pF; V
CC
= 5 V
12
11
78
3.5
40
14
16
61
3.5
40
ns
ns
MHz
pF
pF
HCT
UNIT
f
max
C
I
C
PD
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
µW):
P
D
= C
PD
×
V
CC2
×
f
i
+ ∑
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz
f
o
= output frequency in MHz
∑
(C
L
×
V
CC2
×
f
o
) = sum of outputs
C
L
= output load capacitance in pF
V
CC
= supply voltage in V
2. For HC the condition is V
I
= GND to V
CC
For HCT the condition is V
I
= GND to V
CC
−
1.5 V
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”.
December 1990
2
Philips Semiconductors
Product specification
8-bit serial-in/parallel-out shift register
PIN DESCRIPTION
PIN NO.
1, 2
3, 4, 5, 6, 10, 11, 12, 13
7
8
9
14
SYMBOL
D
sa
, D
sb
Q
0
to Q
7
GND
CP
MR
V
CC
NAME AND FUNCTION
data inputs
outputs
ground (0 V)
74HC/HCT164
clock input (LOW-to-HIGH, edge-triggered)
master reset input (active LOW)
positive supply voltage
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
December 1990
3
Philips Semiconductors
Product specification
8-bit serial-in/parallel-out shift register
74HC/HCT164
Fig.4 Functional diagram.
APPLICATIONS
•
Serial data transfer
FUNCTION TABLE
INPUTS
OPERATING MODES
MR
reset (clear)
L
H
H
H
H
X
↑
↑
↑
↑
CP
X
l
l
h
h
D
sa
X
l
h
l
h
D
sb
L
L
L
L
H
Q
0
OUTPUTS
Q
1
−
Q
7
L
−
L
q
0
q
0
q
0
q
0
−
q
6
−
q
6
−
q
6
−
q
6
shift
Note
1. H = HIGH voltage level
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition
L = LOW voltage level
I = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition
q = lower case letters indicate the state of the referenced input one set-up time prior to the
LOW-to-HIGH clock transition
↑
= LOW-to-HIGH clock transition
Fig.5 Logic diagram.
December 1990
4
Philips Semiconductors
Product specification
8-bit serial-in/parallel-out shift register
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
I
CC
category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; t
r
= t
f
= 6 ns; C
L
= 50 pF
T
amb
(°C)
74HC
SYMBOL PARAMETER
min.
t
PHL
/ t
PLH
propagation delay
CP to Q
n
propagation delay
MR to Q
n
output transition
time
clock pulse width
HIGH or LOW
master reset pulse
width; LOW
removal time
MR to CP
set-up time
D
sa
, D
sb
to CP
hold time
D
sa
, D
sb
to CP
maximum clock
pulse frequency
80
16
14
60
12
10
60
12
10
60
12
10
4
4
4
6
30
35
+25
typ.
41
15
12
39
14
11
19
7
6
14
5
4
17
6
5
17
6
5
8
3
2
−6
−2
−2
23
71
85
max.
170
34
29
140
28
24
75
15
13
100
20
17
75
15
13
75
15
13
75
15
13
4
4
4
5
24
28
−40
to
+85
min.
max.
215
43
37
175
35
30
95
19
16
120
24
20
90
18
15
90
18
15
90
18
15
4
4
4
4
20
24
−40
to
+125
min.
max.
255
51
43
210
42
36
110
22
19
ns
UNIT
74HC/HCT164
TEST CONDITIONS
V
CC
WAVEFORMS
(V)
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
Fig.6
t
PHL
ns
Fig.6
t
THL
/ t
TLH
ns
Fig.6
t
W
ns
Fig.6
t
W
ns
Fig.6
t
rem
ns
Fig.6
t
su
ns
Fig.6
t
h
ns
Fig.6
f
max
MHz
Fig.6
December 1990
5
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