FAST CMOS
12-BIT SYNCHRONOUS
BUS EXCHANGER
Integrated Device Technology, Inc.
IDT54/74FCT162H272AT/CT/ET
FEATURES:
•
•
•
•
•
•
•
•
•
•
•
0.5 MICRON CMOS Technology
Typical t
SK
(o) (Output Skew) < 250ps
Low input and output leakage
≤
1µA (max.)
ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
Packages include 25 mil pitch SSOP, 19.6 mil pitch TSSOP,
15.7 mil pitch TVSOP and 25 mil pitch Cerpack
Extended commercial range of -40°C to +85°C
Balanced Output Drivers:
±24mA
(commercial)
±16mA
(military)
Reduced system switching noise
Typical V
OLP
(Output Ground Bounce) < 0.6V at
V
CC
= 5V, T
A
= 25°C
Bus Hold retains last active bus state during 3-state
Eliminates the need for external pull up resistors
DESCRIPTION:
The FCT162H272AT/CT/ET synchronous tri-port bus ex-
changers are high-speed, bidirectional,12-bit, registered, bus
multiplexers for use in synchronous memory interleaving
applications. All registers have a common clock and use a
clock enable (
CE
xxx) on each data register to control data
sequencing. The output enables and mux select (
OEA
,
OEB
and SEL) are also under synchronous control allowing direc-
tion changes to be edge triggered events.
The tri-port bus exchanger has three 12-bit ports. Data may
be transferred between the A port and either/both of the B
ports. The clock enable (
CE1B
,
CE2B
,
CEA1B
and
CEA2B
)
inputs control the data storage. Both B ports have a common
output enable (
OEB
) to aid in synchronously loading the B
registers from the B port.
The FCT162H272AT/CT/ET have balanced output drive
with current limiting resistors. This offers low ground bounce,
minimal undershoot, and controlled output fall times-reducing
the need for external series terminating resistors.
The FCT162H272AT/CT/ET have "Bus Hold" which re-
tains the input's last state whenever the input goes to high
impedance. This prevents "floating" inputs and eliminates the
need for pull-up/down resistors.
FUNCTIONAL BLOCK DIAGRAM
CEA1B
CLK
CE A-1B
REGISTER
Q
D
12
1B
1:12
CE1B
SEL
OEB
OEA
A
1:12
12
CE2B
12
12
CEA2B
M1
U
X0
12
CONTROL
REGISTER
12
CE 1B-A
REGISTER
D
Q
12
CE 2B-A
REGISTER
Q
D
12
CE A-2B
REGISTER
Q
D
12
2B
1:12
3071 drw 01
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1996
Integrated Device Technology, Inc.
AUGUST 1996
DSC-3071/3
5.5
1
IDT54/74FCT162H272AT/CT/ET
FAST CMOS 12-BIT SYNCHRONOUS TRI-PORT BUS EXCHANGER
MILITARY AND COMMERCIAL TEMPERATURES RANGES
PIN CONFIGURATIONS
CEA1B
CEA2B
2B
3
GND
2B
2
2B
1
V
CC
A
1
A
2
A
3
GND
A
4
A
5
A
6
A
7
A
8
A
9
GND
A
10
A
11
A
12
V
CC
1B
1
1B
2
GND
1B
3
OEA
SEL
1
2
3
4
5
6
7
8
9
10
11
12
13
56
55
54
53
52
51
50
49
48
47
46
45
44
CE1B
CE2B
2B
4
GND
2B
5
2B
6
V
CC
2B
7
2B
8
2B
9
GND
2B
10
2B
11
2B
12
1B
12
1B
11
1B
10
GND
1B
9
1B
8
1B
7
V
CC
1B
6
1B
5
GND
1B
4
OEB
CLK
3071 drw 02
CEA1B
CEA2B
2B
3
GND
2B
2
2B
1
V
CC
A
1
A
2
A
3
GND
A
4
A
5
A
6
A
7
A
8
A
9
GND
A
10
A
11
A
12
V
CC
1B
1
1B
2
GND
1B
3
OEA
SEL
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
CERPACK
TOP VIEW
E56-1
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
CE1B
CE2B
2B
4
GND
2B
5
2B
6
V
CC
2B
7
2B
8
2B
9
GND
2B
10
2B
11
2B
12
1B
12
1B
11
1B
10
GND
1B
9
1B
8
1B
7
V
CC
1B
6
1B
5
GND
1B
4
OEB
CLK
3071 drw 03
14 SO56-1 43
SO56-2
15 SO56-3 42
16
17
18
19
20
21
22
23
24
25
26
27
28
41
40
39
38
37
36
35
34
33
32
31
30
29
SSOP/
TSSOP/TVSOP
TOP VIEW
5.5
2
IDT54/74FCT162H272AT/CT/ET
FAST CMOS 12-BIT SYNCHRONOUS TRI-PORT BUS EXCHANGER
MILITARY AND COMMERCIAL TEMPERATURES RANGES
PIN DESCRIPTION
Signal
A
(1:12)
1B
(1:12)
2B
(1:12
)
CLK
I/O
I/O
I/O
I/O
I
I
I
I
I
I
I
I
Description
Bidirectional Data Port A. Usually connected to the CPU's Address/Data bus.
(1)
Bidirectional Data Port 1B. Usually connected to the even path or even bank of memory.
(1)
Bidirectional Data Port 2B. Usually connected to the odd path or odd bank of memory.
(1)
Clock Input.
Clock Enable Input for the A-1B Register. If
CEA1B
is LOW during the rising edge of CLK, data will be clocked
into register A-1B (Active LOW).
Clock Enable Input for the A-2B Register. If
CEA2B
is LOW during the rising edge of CLK, data will be clocked
into register A-2B (Active LOW).
Clock Enable Input for the 1B-A Register. If
CE1B
is LOW during the rising edge of CLK, data will be clocked into
register 1B-A (Active LOW).
Clock Enable Input for the 2B-A Register. If
CE2B
is LOW during the rising edge of CLK, data will be clocked into
register 2B-A (Active LOW).
1B or 2B Path Selection. When HIGH during the rising edge of CLK, SEL enables data transfer from 1B Port to
A Port. When LOW during the rising edge of CLK, SEL enables data transfer from 2B Port to A Port.
Synchronous Output Enable for A Port (Active LOW).
Synchronous Output Enable for 1B Port and 2B Port (Active LOW).
3071 tbl 01
CEA1B
CEA2B
CE1B
CE2B
SEL
OEA
OEB
NOTES:
1. On FCT162H272T these pins have "Bus Hold". All other pins are standard inputs, outputs or I/Os.
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
Description
Max.
V
TERM(2)
Terminal Voltage with Respect to –0.5 to +7.0
GND
–0.5 to
V
TERM(3)
Terminal Voltage with Respect to
GND
V
CC
+0.5
T
STG
Storage Temperature
–65 to +150
I
OUT
DC Output Current
–60 to +120
Unit
V
V
FUNCTION TABLES
(2)
1B
H
L
X
X
X
X
X
2B
X
X
X
H
L
X
X
Inputs
SEL
CE1B
H
H
H
L
L
L
X
L
L
H
X
X
X
X
CE2B OEA
X
X
X
L
L
H
X
L
L
L
L
L
L
H
CLK
↑
↑
↑
↑
↑
↑
↑
Output
A
H
L
A
(1)
H
L
A
(1)
Z
3071 tbl 04
°
C
mA
3071 tbl 02
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT-
INGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other condi-
tions above those indicated in the operational sections of this specifica-
tion is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
2. All device terminals except FCT162XXXT Output and I/O terminals.
3. Output and I/O terminals for FCT162XXXT.
Inputs
A
H
L
Outputs
CEA1B CEA2B
L
L
L
L
H
H
H
X
X
L
L
H
H
L
L
H
X
X
OEB
L
L
L
L
L
L
L
H
L
CLK
↑
↑
↑
↑
↑
↑
↑
↑
↑
1B
H
L
H
L
B
(1)
B
(1)
B
(1)
Z
Active
2B
H
L
B
(1)
B
(1)
H
L
B
(1)
Z
Active
CAPACITANCE
(T
A
= +25°C, F = 1.0MH
Z
)
Symbol
Parameter
(1)
C
IN
Input
Capacitance
C
I/O
I/O
Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
Typ.
3.5
3.5
Max. Unit
6.0
pF
8.0
pF
3071 tbl 03
H
L
H
L
X
X
X
NOTE:
1. This parameter is measured at characterization but not tested.
3071 tbl 05
NOTES:
1. Output level before the indicated steady-state input conditions were
established.
2. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care
Z = High Impedance
↑
= LOW-to-HIGH Transition
5.5
3
IDT54/74FCT162H272AT/CT/ET
FAST CMOS 12-BIT SYNCHRONOUS TRI-PORT BUS EXCHANGER
MILITARY AND COMMERCIAL TEMPERATURES RANGES
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE (BUS HOLD)
Following Conditions Apply Unless Otherwise Specified:
Commercial: T
A
= –40°C to +85°C, V
CC
= 5.0V
±
10%; Military: T
A
= –55°C to +125°C, V
CC
= 5.0V
±
10%
Symbol
V
IH
V
IL
I
I H
Parameter
Input HIGH Level
Input LOW Level
Input
HIGH
Current
(4)
I
I L
Input
LOW
Current
(4)
I
BHH
I
BHL
I
OZH
I
OZL
V
IK
I
OS
V
H
I
CCL
I
CCH
I
CCZ
Bus Hold
Standard Input
(5)
Standard I/O
(5)
Bus-Hold Input
Bus-Hold I/O
Standard Input
(5)
Standard I/O
(5)
Bus-Hold Input
Bus-Hold I/O
Bus-Hold Input
V
CC
= Min.
V
I
= 2.0V
V
I
= 0.8V
V
CC
= Max.
V
CC
= Min., I
IN
= –18mA
V
CC
= Max., V
O
= GND
(3)
—
Test Conditions
(1)
Guaranteed Logic HIGH Level
Guaranteed Logic LOW Level
V
CC
= Max.
V
I
= V
CC
Min.
2.0
—
—
—
—
—
Typ.
(2)
—
—
—
—
—
—
—
—
—
—
—
—
—
—
–
0.7
–
140
Max.
—
Unit
V
V
0.8
±
1
±
1
±
100
±
100
±
1
±
1
±
100
±
100
—
—
µ
A
V
I
= GND
—
—
—
—
–50
+50
—
—
—
–80
—
—
µ
A
Sustain
Current
(4)
High Impedance Output Current
(3-State Output pins)
(5,6)
Clamp Diode Voltage
Short Circuit Current
Input Hysteresis
Quiescent Power Supply Current
V
O
= 2.7V
V
O
= 0.5V
±
1
±
1
–
1.2
–
225
—
µ
A
V
mA
mV
100
5
V
CC
= Max., V
IN
= GND or V
CC
500
µ
A
3071 tbl 06
OUTPUT DRIVE CHARACTERISTICS FOR FCT162H272T
Symbol
I
ODL
I
ODH
V
OH
V
OL
Parameter
Output LOW Current
Output HIGH Current
Output HIGH Voltage
Output LOW Voltage
Test Conditions
(1)
V
CC
= 5V, V
IN
= V
IH
or V
IL,
V
OUT
= 1.5V
(3)
V
CC
= 5V, V
IN
= V
IH
or V
IL,
V
OUT
= 1.5V
(3)
V
CC
= Min.
V
IN
= V
IH
or V
IL
V
CC
= Min.
V
IN
= V
IH
or V
IL
I
OH
= –16mA MIL.
I
OH
= –24mA COM'L.
I
OL
= 16mA MIL.
I
OL
= 24mA COM'L.
Min.
60
–60
2.4
—
Typ.
(2)
115
–115
3.3
0.3
Max.
200
–200
—
0.55
Unit
mA
mA
V
V
3071 lnk 08
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient.
3. Not more than one output should be tested at one time. Duration of the test should not exceed one second.
4. Pins with Bus Hold are identified in the pin description.
5. The test limit for this parameter is
±
5µA at T
A
= –55°C.
6. Does not include Bus Hold I/O pins.
5.5
4
IDT54/74FCT162H272AT/CT/ET
FAST CMOS 12-BIT SYNCHRONOUS TRI-PORT BUS EXCHANGER
MILITARY AND COMMERCIAL TEMPERATURES RANGES
POWER SUPPLY CHARACTERISTICS
Symbol
∆I
CC
I
CCD
Parameter
Quiescent Power Supply Current
TTL Inputs HIGH
Dynamic Power Supply Current
(4)
Test Conditions
(1)
V
CC
= Max.
V
IN
= 3.4V
(3)
V
CC
= Max.
Outputs Open
One Output Port Enabled
CExx
= GND
One Input Bit Toggling
One Output Bit Toggling
50% Duty Cycle
V
CC
= Max.
Outputs Open
fi = 10MHz
50% Duty Cycle
One Output Port Enabled
CExx
= GND
One Input Bit Toggling
One Output Bit Toggling
V
CC
= Max.
Outputs Open
fi = 2.5MHz
50% Duty Cycle
One Output Port Enabled
CExx
= GND
Twelve Input Bits Toggling
Twelve Output Bits Toggling
Min.
—
—
Typ.
(2)
0.5
60
Max.
1.5
100
Unit
mA
µA/
MHz
V
IN
= V
CC
V
IN
= GND
I
C
Total Power Supply Current
(6)
V
IN
= V
CC
V
IN
= GND
V
IN
= 3.4V
V
IN
= GND
—
0.6
1.5
mA
—
0.9
2.3
V
IN
= V
CC
V
IN
= GND
V
IN
= 3.4V
V
IN
= GND
—
1.8
3.5
(5)
—
4.8
12.5
(5)
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 5.0V, +25°C ambient.
3. Per TTL driven input (V
IN
= 3.4V). All other inputs at V
CC
or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the I
CC
formula. These limits are guaranteed but not tested.
6. I
C
= I
QUIESCENT
+ I
INPUTS
+ I
DYNAMIC
I
C
= I
CC
+
∆I
CC
D
H
N
T
+ I
CCD
(f
CP
N
CP
/2 + f
i
N
i
)
I
CC
= Quiescent Current (I
CCL
,
I
CCH
and I
CCZ
)
∆I
CC
= Power Supply Current for a TTL High Input (V
IN
= 3.4V)
D
H
= Duty Cycle for TTL Inputs High
N
T
= Number of TTL Inputs at D
H
I
CCD
= Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
f
CP
= Clock Frequency for Register Devices (Zero for Non-Register Devices)
N
CP
= Number of Clock Inputs at f
CP
f
i
= Input Frequency
N
i
= Number of Inputs at f
i
3071 tbl 09
5.5
5
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