FAST CMOS 18-BIT
R/W BUFFER
Integrated Device Technology, Inc.
IDT54/74FCT162701T/AT
FEATURES:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
0.5 MICRON CMOS Technology
Typical t
SK
(o) (Output Skew) < 250ps
Low input and output leakage
≤1µA
(max.)
ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
Packages include 25 mil pitch SSOP, 19.6 mil pitch TSSOP,
15.7 mil pitch TVSOP and 25 mil pitch Cerpack
Extended commercial range of -40°C to +85°C
Balanced Output Drivers:
±24mA
(commercial),
±16mA
(military)
Reduced system switching noise
Typical V
OLP
(Output Ground Bounce) < 0.6V at
V
CC
= 5V, T
A
= 25°C
Ideal for new generation x86 write-back cache solutions
Suitable for modular x86 architectures
Four deep write FIFO
Latch in read path
Synchronous FIFO reset
DESCRIPTION:
The FCT162701T/AT is an 18-bit Read/Write buffer with
a four deep FIFO and a read-back latch. It can be used as
a read/write buffer between a CPU and memory or to
interface a high-speed bus and a slow peripheral. The A-
to-B (write) path has a four deep FIFO for pipelined opera-
tions. The FIFO can be reset and a FIFO full condition is
indicated by the full flag (
FF
). The B-to-A (read) path has a
latch. A HIGH on LE, allows data to flow transparently from
B-to-A. A LOW on LE allows the data to be latched on the
falling edge of LE.
The FCT162701T/AT has a balanced output drive with
series termination. This provides low ground bounce,
minimal undershoot and controlled output edge rates.
FUNCTIONAL BLOCK DIAGRAM
A
1-18
18
OEBA
RESET
CLK
WCE
RCE
FF
FIFO
(4 deep)
LATCH
LE
OEAB
18
2915 drw 01
B
1-18
The IDT logo is a registered trademark of Integrated Device Techology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1996
Integrated Device Technology, Inc.
AUGUST 1996
DSC-2915/3
5.15
1
IDT54/74FCT162701T/AT
FAST CMOS 18-BIT R/W BUFFER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
OEAB
WCE
A
1
GND
A
2
A
3
V
CC
A
4
A
5
A
6
GND
A
7
A
8
A
9
A
10
A
11
A
12
GND
A
13
A
14
A
15
V
CC
A
16
A
17
GND
A
18
OEBA
LE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
SO56-1 43
SO56-2
SO56-3 42
41
40
39
38
37
36
35
34
33
32
31
30
29
RCE
CLK
B
1
GND
B
2
B
3
V
CC
B
4
B
5
B
6
GND
B
7
B
8
B
9
B
10
B
11
B
12
GND
B
13
B
14
B
15
V
CC
B
16
B
17
GND
B
18
FF
RESET
OEAB
WCE
A
1
GND
A
2
A
3
V
CC
A
4
A
5
A
6
GND
A
7
A
8
A
9
A
10
A
11
A
12
GND
A
13
A
14
A
15
V
CC
A
16
A
17
GND
A
18
OEBA
LE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
CERPACK
TOP VIEW
E56-1
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
RCE
CLK
B
1
GND
B
2
B
3
V
CC
B
4
B
5
B
6
GND
B
7
B
8
B
9
B
10
B
11
B
12
GND
B
13
B
14
B
15
V
CC
B
16
B
17
GND
B
18
FF
RESET
SSOP/
TSSOP/TVSOP
TOP VIEW
2915 drw 02
2915 drw 03
5.15
2
IDT54/74FCT162701T/AT
FAST CMOS 18-BIT R/W BUFFER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN DESCRIPTION
Pin Names
A
1-18
B
1-18
CLK
I/O
I/O
I/O
I
18 bit I/O port.
18 bit I/O port.
Clock for write path FIFO. Clocks data into FIFO when
WCE
is low, clocks data out of FIFO when
RCE
is
low. When FIFO is full all further writes to the FIFO are inhibited. When FIFO is empty all reads from the
FIFO are inhibited. CLK also resets the FIFO when
RESET
is low.
Enable pin for FIFO input clock.
Enable pin for FIFO output clock.
Write path FIFO full flag. Goes low when FIFO is full.
Synchronous FIFO reset - when low CLK resets the FIFO. The FIFO pointers are initialized to the
"empty" condition and FIFO output is forced high (all ones). The FIFO full flag (
FF
) will be high
immediately after reset.
Output Enable pin for B port.
Output Enable pin for A port.
Read path latch enable pin. When high, data flows transparently from B port to A port, B data is latched
on the falling edge of LE.
2915 tbl 01
Description
WCE
RCE
FF
RESET
OEAB
OEBA
LE
I
I
O
I
I
I
I
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
Description
Max.
(2)
Terminal Voltage with Respect to –0.5 to +7.0
V
TERM
GND
V
TERM(3)
Terminal Voltage with Respect to
–0.5 to
GND
V
CC
+0.5
T
STG
Storage Temperature
–65 to +150
I
OUT
DC Output Current
–60 to +120
Unit
V
V
°C
mA
CAPACITANCE
(T
A
= +25°C, f = 1.0MHz)
Symbol
Parameter
(1)
C
IN
Input
Capacitance
C
I/O
I/O
Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
Typ.
3.5
3.5
Max. Unit
6.0
pF
8.0
pF
2915 lnk 03
NOTE:
1. This parameter is measured at characterization but not tested.
2915 lnk 02
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT-
INGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
2. All device terminals except FCT162XXXT Output and I/O terminals.
3. Output and I/O terminals for FCT162XXXT.
5.15
3
IDT54/74FCT162701T/AT
FAST CMOS 18-BIT R/W BUFFER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
FUNCTIONAL DESCRIPTION:
This device is useful as a read/write buffer for modular high
end designs. It provides multi-level buffering in the write path
and single deep buffering in the read path, and is suited to
write back cache implementation. The read path provides a
transparent latch.
The four deep FIFO uses one clock with two clock enable
pins,
WCE
and
RCE
to clock data in and out. The FIFO has
an external full flag which goes LOW when the FIFO is full.
Internal read and write pointers keep track of the words stored
in the FIFO. A write attempt to a full FIFO is ignored. An
attempt to read from an empty FIFO will have no effect and the
last read data remains at the output of the FIFO. The FIFO
may be reset by the synchronous
RESET
input. This resets
the read and write pointers to the original "empty" condition
and also sets all B outputs = 1. Simultaneous read and write
attempts (clock data into FIFO as well as clock data out of
FIFO) are possible except on FIFO empty and full boundaries.
When the FIFO is empty, and a simultaneous read and write
is attempted, the read is ignored while the write is executed.
If the same is attempted when the FIFO is full, the write is
ignored while the read is executed. Normal operation of the
four deep FIFO in the write path is independent of the read
path operation.
Power, ground and data pin positions on the FCT162701T
match those on the FCT16501T/162501T, allowing an easy
upgrade.
APPLICATIONS: 486 INTERFACE
CacheRAM
Coprocessor
i486
FCT162701T
A
B
DRAM
W/R
CLK
CLK,WCE,
RCE, RST
PAL
LE,OEBA,
OEAB
2915 drw 04
Figure 1. FCT162701T Application Example
5.15
4
IDT54/74FCT162701T/AT
FAST CMOS 18-BIT R/W BUFFER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Commercial: T
A
= -40°C to +85°C, V
CC
= 5.0V
±
10%; Military: T
A
= -55°C to +125°C, V
CC
= 5.0V
±
10%
Symbol
V
IH
V
IL
I
I H
I
I L
I
OZH
I
OZL
V
IK
I
OS
V
H
I
CCL
I
CCH
I
CCZ
Parameter
Input HIGH Level
Input LOW Level
Input HIGH Current (Input pins)
(5)
Input HIGH Current (I/O pins)
(5)
Input LOW Current (Input pins)
(5)
Input LOW Current (I/O pins)
(5)
High Impedance Output Current
(3-State Output pins)
(5)
Clamp Diode Voltage
Short Circuit Current
Input Hysteresis
Quiescent Power Supply Current
V
CC
= Min., I
IN
= –18mA
V
CC
= Max., V
O
= GND
(3)
—
Test Conditions
(1)
Guaranteed Logic HIGH Level
Guaranteed Logic LOW Level
V
CC
= Max.
V
I
= V
CC
V
I
= GND
V
CC
= Max.
V
O
= 2.7V
V
O
= 0.5V
Min.
2.0
—
—
—
—
—
—
—
—
–80
—
—
Typ.
(2)
—
—
—
—
—
—
—
—
–
0.7
–
140
Max.
—
Unit
V
V
µA
0.8
±1
±1
±1
±1
±1
±1
–
1.2
–
225
—
µA
V
mA
mV
µA
100
5
V
CC
= Max., V
IN
= GND or V
CC
500
2915 lnk 04
OUTPUT DRIVE CHARACTERISTICS
Symbol
I
ODL
I
ODH
V
OH
V
OL
Parameter
Output LOW Current
Output HIGH Current
Output HIGH Voltage
Output LOW Voltage
Test Conditions
(1)
V
CC
= 5V, V
IN
= V
IH
or V
IL,
V
OUT
= 1.5V
(3)
V
CC
= 5V, V
IN
= V
IH
or V
IL,
V
OUT
= 1.5V
(3)
V
CC
= Min.
V
IN
= V
IH
or V
IL
V
CC
= Min.
V
IN
= V
IH
or V
IL
I
OH
= –16mA MIL.
I
OH
= –24mA COM'L.
I
OL
= 16mA MIL.
I
OL
= 24mA COM'L.
Min.
60
–60
2.4
—
Typ.
(2)
115
–115
3.3
0.3
Max.
200
–200
—
0.55
Unit
mA
mA
V
V
2915 lnk 05
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient.
3. Not more than one output should be tested at one time. Duration of the test should not exceed one second.
4. Duration of the condition can not exceed one second.
5. The test limit for this parameter is
±
5µA at T
A
= –55°C.
5.15
5
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
