Oscillator SMD, spread spectrum, programmable
Features:
Supply voltage 2,5V + 3,3V
Different spread widths available
Short delivery time
APSSO 7050
APSSO 5032
Specifications
Frequency range
Frequency stability
Operating temperature
Storage temperature
Programmable voltage
1 ~ 166 MHz
Programmable voltage
1 ~ 200 MHz
Aging (ppm / Year), Ta = 25C, Vdd = 5 / 3.3 V
Programmable output level
APSO 7050 / APSO 5032
1.5MHz ~ 200MHz
±25ppm ~ ±100ppm
-40°C ~ +85°C
-55°C ~ +125°C
2.5V ±10%
3.3V ±10%
±5ppm
HCMOS
Remarks
Please specify
Please specify
Please specify
Drawing
APSO 5032
APSO 7050
Dimensions in mm
Operating conditions
Description
Supply voltage
Vdd
Rise Time
Vdd
HCMOS max capacitive load on outputs for CMOS levels
Frequency: <40MHz
Frequency: <40-200MHz
Min
2.25
100
Max
3.6
Unit
V
µS
pF
pF
30
15
Order key
O
Part
O=Oscillator
- 10.000000M - APSO 7050
Frequency
M=MHz
Type/Package
APQO= programmable QO
7050=SMD 7x5
- 50
Tolerance
±ppm
- 2.5
Voltage
2.5=2.5Volt
3.3=3.3Volt
-A
Temperature
A=
0°C ~ +70°C
/ T
Option
T= Tristate
P= Power
down
/ C
Spread
/
Packaging
blank = tube
B= -10°C ~ +60°C
C= -10°C ~ +70°C
D= -20°C ~ +70°C
E= -40°C ~ +85°C
please
see
table 1
auris-GmbH
office@auris-gmbh.de www.auris-gmbh.de
All specifications are subject to change without notice.
4.13
Oscillator SMD, spread spectrum, programmable
APSSO 7050
APSSO 5032
Output clock switching characteristics
Description
Duty cycle
Test conditions
2.25V~3.6V Vdd
0.2-0.8Vdd, 2.25-3.6 Vdd, Cl=30
0.2-0.8Vdd, 2.25-3.6Vdd, Cl=15
From power on
Min
45
Typ
Max
55
4.0
2.4
10
Unit
%
ns
ns
ms
HCMOS @ Vdd/2
Output clock rise / fall
Start up time
3
Electrical characteristics
Discription
Input characteristics (Pin 1)
TO Tri-state or power-down
Test conditions
VIL, Low-level input voltage
Min
Typ
Max
0.2 Vdd
Unit
V
V
µA
µA
V
V
mA
µA
3.0 ~ 3.6 V Vdd
3.0 ~ 3.6 V Vdd
V
IN
= 0V
V
IN
= Vdd
3.0 V ~ 3.6 V Vdd, 8 mA I
OL
2.25 V ~ 3.6 V Vdd, -8 mA I
OL
2.25 ~ 3.6 Vdd, O
UTPUT FREQ
≤
200 MHz
2.25 ~ 3.6V Vdd, V
IN
= 0.7V
3.6V Vdd
Output is tri-stated
Output is power down
0.7 Vdd
V
IH
, High-level input voltage
TO Enable output or no connect
I
IL
, Input low current
I
IH
, Input high current
Output characteristics VOL, Low-level output voltage
80
10
0.4
Vdd - 0.4
50
70
20
35
90
VOHCMOS, High-level CMOS voltage
Power supply current (unloaded)
Input pull-up resistor
Tri-state leakage current
Output enable mode
A
B
C
D
E
F
G
H
Table 1
spread
± 0.125%
± 0.250%
± 0.375%
± 0.500%
± 0.625%
± 0.750%
± 0.875%
± 1.000%
I
K
M
O
P
R
S
T
spread
± 1.125%
± 1.250%
± 1.375%
± 1.500%
± 1.625%
± 1.750%
± 1.875%
± 2.000%
auris-GmbH
office@auris-gmbh.de www.auris-gmbh.de
All specifications are subject to change without notice.
4.14
FPGA/CPLD
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