LD6935 series
Dual low-dropout regulators, high PSRR, 300 mA
Rev. 1 — 29 May 2013
Preliminary data sheet
1. Product profile
1.1 General description
The LD6935 series consists of small-size dual Low DropOut regulators (LDO). Each
device delivers two times 300 mA with a typical voltage drop of 240 mV at 300 mA for
each LDO. Each device offers two individual fixed nominal output voltages (V
O(nom)
) from
1.2 V to 3.6 V.
The LDO has an integrated Soft start to control the inrush current during start-up. The
output states when disabled can be high-ohmic 3-state or auto discharge. Optionally a
delayed output circuit is available for the second output. The devices are available in
DFN1612-8 (SOT1225) plastic package with a height of 0.4 mm.
1.2 Features and benefits
Extremely low standby current in shutdown mode ( 0.1
A)
Low quiescent current
Low output noise
Fast turn-on time
High Power Supply Rejection Ratio (PSRR)
Auto discharge or high-ohmic mode for output states when disabled
Delayed output circuit for second LDO (optional)
DFN1612-8 (SOT1225) leadless package 1.6
1.2
0.4 mm
Pb-free, Restriction of Hazardous Substances (RoHS) compliant, free of halogen and
antimony (Dark Green compliant)
1.3 Applications
Smartphones
Mobile handsets
Digital still cameras
Tablet PCs
Mobile internet devices
Portable media players
1.4 Quick reference data
I
O
= 300 mA for each LDO
PSRR = 80 dB at 1 kHz
RMS noise V
n(o)RMS
= 60
V
at 10 Hz to 100 kHz
t
startup(reg)
= 150
s
V
I
= 1.75 V to 5.5 V
V
O
= 1.2 V to 3.6 V (fixed value)
Dropout voltage V
do
= 240 mV
at I
O
= 300 mA for each LDO
Quiescent current I
q
= 2
35
A
at
I
O
= 0 mA
NXP Semiconductors
LD6935 series
Dual low-dropout regulators, high PSRR, 300 mA
2. Pinning information
2.1 Pinning
Fig 1.
Pin configuration for DFN1612-8 (SOT1225)
2.2 Pin description
Table 1.
Symbol
GND
OUT1
OUT2
GND
EN2
IN2
IN1
EN1
i.c.
[1]
Pin description for DFN1612-8 (SOT1225)
Pin
1
2
3
4
5
6
7
8
TAB
Description
supply ground
regulator 1 output voltage
regulator 2 output voltage
supply ground
regulator 2 enable input
regulator 2 supply voltage input
regulator 1 supply voltage input
regulator 1 enable input
internal connected
[1]
The TAB is GND level (it is placed on the reverse side of the IC).
It is recommended to connect the TAB to GND. Leaving it unconnected is also allowed but it may result in
lower thermal performance.
3. Ordering information
Table 2.
Ordering information
Package
Name
LD6935L
Description
Version
DFN1612-8 plastic extremely thin small outline package; no leads; SOT1225
8 terminals; body 1.6
1.2
0.4 mm
Type number
LD6935_SER
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Preliminary data sheet
Rev. 1 — 29 May 2013
2 of 24
NXP Semiconductors
LD6935 series
Dual low-dropout regulators, high PSRR, 300 mA
3.1 Ordering options
Further output voltage information available on request; see
Section 19 “Contact
information”.
Table 3.
Type number and nominal output voltage of high-ohmic output
Nominal output voltage V
O(nom)
OUT1
LD6935L/2828H
LD6935L/3318H
Table 4.
2.8 V
3.3 V
OUT2
2.8 V
1.8 V
Type number
Type number and nominal output voltage of pull-down output
Nominal output voltage V
O(nom)
OUT1
OUT2
2.8 V
2.8 V
1.8 V
2.8 V
3.3 V
1.8 V
2.8 V
3.3 V
3.3 V
3.3 V
Type number
LD6935L/1828P
LD6935L/2828P
LD6935L/3318P
LD6935L/3328P
LD6935L/3333P
Table 5.
Type number and nominal output voltage of pull-down output with delay circuit
Nominal output voltage V
O(nom)
OUT1
OUT2
1.8 V
3.1 V
Type number
LD6935L/3118PD
LD6935_SER
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Preliminary data sheet
Rev. 1 — 29 May 2013
3 of 24
NXP Semiconductors
LD6935 series
Dual low-dropout regulators, high PSRR, 300 mA
4. Block diagram
Fig 2.
Block diagram dual LDO with auto discharge function (-P and -PD versions)
Fig 3.
Block diagram dual LDO with high-ohmic output (-H version)
LD6935_SER
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Preliminary data sheet
Rev. 1 — 29 May 2013
4 of 24
NXP Semiconductors
LD6935 series
Dual low-dropout regulators, high PSRR, 300 mA
5. Limiting values
Table 6.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to
GND (ground = 0 V).
Symbol
V
I
V
EN
V
O
P
tot
T
stg
T
j
T
amb
V
ESD
Parameter
input voltage
voltage on pin EN
output voltage
total power dissipation
storage temperature
junction temperature
ambient temperature
electrostatic discharge
voltage
human body model
machine model
[2]
[3]
Conditions
4 ms transient
4 ms transient
4 ms transient
[1]
Min
0.5
0.5
0.5
-
55
40
40
-
-
Max
+6.0
+6.0
+6.0
740
+150
+125
+85
2
200
Unit
V
V
V
mW
C
C
C
kV
V
Pin IN1, IN2, EN1 and EN2
Pin OUT1 and OUT2
[1]
The (absolute) maximum power dissipation depends on the junction temperature T
j
. Higher power
dissipation is allowed with lower ambient temperatures. The conditions to determine the specified values
are T
amb
= 25
C
and the use of a two-layer Printed-Circuit Board (PCB).
According to JESD22-A114F.
According to JESD22-A115C.
[2]
[3]
6. Recommended operating conditions
Table 7.
Operating conditions
Voltages are referenced to GND (ground = 0 V).
Symbol
T
amb
T
j
V
I
C
ext(IN)
V
EN
V
O
C
L(ext)
[1]
Parameter
ambient temperature
junction temperature
input voltage
external capacitance on pin IN
voltage on pin EN
output voltage
external load capacitance
Conditions
Min
40
-
1.75
[1]
Max
+85
+125
5.5
-
V
I
V
I
+ 0.3
-
Unit
°C
°C
V
F
V
V
F
Pin IN1 and IN2
1.0
0
0
1.0
Pin EN1 and EN2
Pin OUT1 and OUT2
See
Section 10.1 “Input and output capacitor values”.
LD6935_SER
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Preliminary data sheet
Rev. 1 — 29 May 2013
5 of 24
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