The UT54ACS02E and UT54ACTS02E are quadruple, two-
input NOR gates. The circuits perform the Boolean functions
Y = A + B or Y = A
⋅
B in positive logic.
The devices are characterized over the full HiRel temperature
range of -55°C to +125°C.
FUNCTION TABLE
INPUTS
A
H
X
L
B
X
H
L
OUTPUT
Y
L
L
H
PINOUT
14-Lead Flatpack
Top View
Y1
A1
B1
Y2
A2
B2
V
SS
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V
DD
Y4
B4
A4
Y3
B3
A3
LOGIC SYMBOL
LOGIC DIAGRAM
A1 (2)
B1 (3)
A2 (5)
(6)
B2
(8)
A3
(9)
B3
(11)
A4
(12)
B4
≥1
(1)
(4)
(10)
(13)
Y1
Y2
Y3
Y4
A1
B1
A2
B2
A3
B3
A4
B4
Y4
Y3
Y1
Y2
Note:
1. Logic symbol in accordance with ANSI/IEEE standard 91-1984 and IEC
Publication 617-12.
1
OPERATIONAL ENVIRONMENT
1
PARAMETER
Total Dose
SEU Threshold
2
SEL Immune
Neutron Fluence
Notes:
1. Logic will not latchup during radiation exposure within the limits defined in the table.
2. Device storage elements are immune to SEU affects.
LIMIT
1.0E6
108
120
1.0E14
UNITS
rads(Si)
MeV-cm
2
/mg
MeV-cm
2
/mg
n/cm
2
ABSOLUTE MAXIMUM RATINGS
1
SYMBOL
V
DD
V
I/O
T
STG
T
J
T
LS
Θ
JC
I
I
P
D2
PARAMETER
Supply voltage
Voltage any pin
Storage Temperature range
Maximum junction temperature
Lead temperature (soldering 5 seconds)
Thermal resistance junction to case
DC input current
Maximum package power dissipation
permitted @ Tc=125
o
C
LIMIT
-0.3 to 6.0
-0.3 to V
DD
+ 0.3
-65 to +150
+175
+300
15.5
±10
3.2
UNITS
V
V
°C
°C
°C
°C/W
mA
W
Note:
1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device at
these or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
2. Per MIL-STD-883, method 1012.1, Section 3.4.1, P
D
= (T
j(max)
- T
c(max)
) /
Θ
jc
RECOMMENDED OPERATING CONDITIONS
SYMBOL
V
DD
V
IN
T
C
PARAMETER
Supply voltage
Input voltage any pin
Temperature range
LIMIT
3.0 to 5.5
0 to V
DD
-55 to + 125
UNITS
V
V
°C
2
DC ELECTRICAL CHARACTERISTICS FOR THE UT54ACS02E
7
( V
DD
= 3.0V to 5.5V; V
SS
= 0V
6
; -55°C < T
C
< +125°C)
SYMBOL
V
IL
V
IH
I
IN
V
OL
DESCRIPTION
Low-level input voltage
1
High-level input voltage
1
Input leakage current
Low-level output voltage
3
CONDITION
V
DD
from 3.0V to 5.5V
V
DD
from 3.0V to 5.5V
V
IN
= V
DD
or V
SS
I
OL
= 100μA
V
DD
from 3.0V to 5.5V
V
OH
High-level output voltage
3
I
OH
= -100μA
V
DD
from 3.0V to 5.5V
I
OS1
Short-circuit output current
2 ,4
V
O
= V
DD
and V
SS,
V
DD
from 4.5V to 5.5V
I
OS2
Short-circuit output current
2 ,4
V
O
= V
DD
and V
SS,
V
DD
from 3.0V to 3.6V
I
OL1
Low level output current
(sink)
9
V
IN
= V
DD
or V
SS
V
OL
= 0.4V
V
DD
from 4.5V to 5.5V
I
OL2
Low level output current
(sink)
9
V
IN
= V
DD
or V
SS
V
OL
= 0.4V
V
DD
from 3.0V to 3.6V
I
OH1
High level output current
(source)
9
V
IN
= V
DD
or V
SS
V
OH
= V
DD
-0.4V
V
DD
from 4.5V to 5.5V
I
OH2
High level output current
(source)
9
V
IN
= V
DD
or V
SS
V
OH
= V
DD
-0.4V
V
DD
from 3.0V to 3.6V
P
total1
P
total2
I
DDQ
C
IN
C
OUT
Power dissipation
2, 8
Power dissipation
2, 8
Quiescent Supply Current
Input capacitance
5
Output capacitance
5
C
L
= 50pF, V
DD
= 4.5V to 5.5V
C
L
= 50pF, V
DD
= 3.0V to 3.6V
V
IN
= V
DD
or V
SS,
V
DD
from 3.0V to 5.5V
ƒ
= 1MHz, V
DD
= 0V
ƒ
= 1MHz, V
DD
= 0V
1.8
0.72
10
15
15
mW/
MHz
mW/
MHz
μA
pF
pF
-6
mA
-8
mA
6
mA
8
mA
-100
100
mA
-200
200
mA
V
DD
- 0.25
V
0.7 V
DD
-1
1
0.25
MIN
MAX
0.3 V
DD
UNIT
V
V
μA
V
3
Notes:
1. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: V
IH
= V
IH
(min) + 20%, - 0%; V
IL
= V
IL
(max) + 0%, -
50%, as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above specified range, but are
guaranteed to V
IH
(min) and V
IL
(max).
2. Supplied as a design limit but not guaranteed or tested.
3. Per MIL-PRF-38535, for current density
≤5.0E5
amps/cm
2
, the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765pF/
MHz.
4. Not more than one output may be shorted at a time for maximum duration of one second.
5. Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and V
SS
at
frequency of 1MHz and a signal amplitude of 50mV rms maximum.
6. Maximum allowable relative shift equals 50mV.
7. All specifications valid for the maximum radiation dose available for the respective device types.
8. Power dissipation specified per switching output.
9. Guaranteed by characterization, but not tested.
4
AC ELECTRICAL CHARACTERISTICS FOR THE UT54ACS02E
2
(V
DD
= 3.0V to 5.5V; V
SS
= 0V
1
, -55°C < T
C
< +125°C)
SYMBOL
t
PLH
PARAMETER
Input to Yn
CONDITION
C
L
= 50pF
V
DD
3.0V to 3.6V
4.5V to 5.5V
MINIMUM
1
1
1
1
MAXIMUM
15
7
17
6
UNIT
ns
t
PHL
Input to Yn
C
L
= 50pF
3.0V to 3.6V
4.5V to 5.5V
ns
Notes:
1. Maximum allowable relative shift equals 50mV.
2. All specifications valid for the maximum radiation dose available for the respective device types.
FPGA/CPLD
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
