1 Megabit (128K x 8-Bit) EEPROM
V
CC
V
SS
RES
OE
CE
WE
RES
A0
A6
Address
Buffer and
Latch
Y Decoder
Y Gating
I/O Buffer and
Input Latch
Control Logic Timing
High Voltage
Generator
I/O0
I/O7
RDY/Busy
28C011T
A7
A16
X Decoder
Memory Array
Data Latch
Memory
Logic Diagram
F
EATURES
:
• 128k x 8-bit EEPROM
• R
AD
-P
AK
® radiation hardened against natural space radia-
tion
• Total dose hardness:
- > 100 krad (Si), depending upon space mission
• Excellent Single Event Effects:
- No Latchup > 120 MeV/mg/cm
2
- SEU > 90 MeV/mg/cm
2
read mode
• Package:
- 32-pin R
AD
-P
AK
® flat pack package
- JEDEC-approved byte-wide pinout
• High speed:
- 120, 150, and 200 ns maximum access times available
• High endurance:
- 10,000 cycles/byte, 10-year data retention
• Page write mode:
- 1 to 128 byte page
• Low power dissipation
- 20 mW/MHz active (typical)
- 110 µW standby (maximum)
• Screening per TM 5004
• QCI per TM5005
D
ESCRIPTION
:
Maxwell Technologies
’ 28C011T high-density 1 Megabit
(128K x 8-Bit) EEPROM microcircuit features a greater than
100 krad (Si) total dose tolerance, depending upon space mis-
sion. The 28C011T is capable of in-system electrical byte and
page programmability. It has a 128-byte page programming
function to make its erase and write operations faster. It also
features Data Polling and a Ready / Busy signal to indicate the
completion of erase and programming operations. In the
28C011T, hardware data protection is provided with the RES
pin, in addition to noise protection on the WE signal and write
inhibit on power on and off. Software data protection is imple-
mented using the JEDEC optional standard algorithm.
Maxwell Technologies' patented RAD-PAK® packaging tech-
nology incorporates radiation shielding in the microcircuit
package. It eliminates the need for box shielding while provid-
ing the required radiation shielding for a lifetime in orbit or
space mission. In a GEO orbit, R
AD
-P
AK
provides greater than
100 krad (Si) radiation dose tolerance. This product is avail-
able with screening up to Class S.
1000580
12.19.01 Rev 7
All data sheets are subject to change without notice
1
(858) 503-3300- Fax: (858) 503-3301- www.maxwell.com
©2001 Maxwell Technologies
All rights reserved.
1 Megabit (128K x 8-Bit) EEPROM
T
ABLE
1. 28C011T P
INOUT
D
ESCRIPTION
P
IN
12-4, 27, 26, 23,
25, 4,28, 3, 31, 2
13-21
24
22
29
32
16
1
30
S
YMBOL
A0-A16
I/O 0 - 7
OE
CE
WE
V
CC
V
SS
RDY/BUSY
RES
D
ESCRIPTION
Address
Data Input/Output
Output Enable
Chip Enable
Write Enable
Power Supply
Ground
Ready/Busy
Reset
28C011T
Memory
T
ABLE
2. 28C011T A
BSOLUTE
M
AXIMUM
R
ATINGS
P
ARAMETER
Supply Voltage (Relative to V
SS
)
Input Voltage (Relative to V
SS
)
Operating Temperature Range
Storage Temperature Range
1. V
IN
min = -3.0V for pulse width < 50ns.
SYMBOL
MIN
MAX
UNITS
V
CC
V
IN
T
OPR
T
STG
-0.6
-0.5
1
-55
-65
+7.0
+7.0
+125
+150
V
V
°
C
°
C
T
ABLE
3. D
ELTA
L
IMITS
P
ARAMETER
I
CC
1
I
CC
2
I
CC
3
I
LI
I
LO
V
ARIATION
±10%
±10%
±10%
±10%
±10%
1000580
12.19.01 Rev 7
All data sheets are subject to change without notice
2
©2001 Maxwell Technologies
All rights reserved.
1 Megabit (128K x 8-Bit) EEPROM
T
ABLE
4. 28C011T R
ECOMMENDED
O
PERATING
C
ONDITIONS
P
ARAMETER
Supply Voltage
Input Voltage
RES_PIN
Thermal Impedance — Flat Package
Operating Temperature Range
1. V
IL
min = 1.0V for pulse width < 50 ns
S
YMBOL
V
CC
V
IL
V
IH
V
H
M
IN
4.5
-0.3
1
2.2
V
CC
-0.5
--
-55
28C011T
M
AX
5.5
0.8
V
CC
+0.3
V
CC
+1
2.17
+125
°C/W
°
C
U
NITS
V
V
Θ
JC
T
OPR
T
ABLE
5. 28C011T C
APACITANCE
(T
A
= 25
°
C, f = 1 MHZ)
P
ARAMETER
Input Capacitance: V
IN
= 0V
1
Output Capacitance: V
OUT
= 0V
1
1. Guaranteed by design.
S
YMBOL
C
IN
C
OUT
M
IN
--
--
M
AX
6
12
U
NITS
pF
pF
Memory
T
ABLE
6. 28C011T DC E
LECTRICAL
C
HARACTERISTICS
(V
CC
= 5V ± 10%, T
A
= -55
TO
+125
°
C,
UNLESS OTHERWISE SPECIFIED
)
P
ARAMETER
Input Leakage Current
Output Leakage Current
Standby V
CC
Current
Operating V
CC
Current
T
EST
C
ONDITION
V
CC
= 5.5V, V
IN
= 5.5V
V
CC
= 5.5V, V
OUT
= 5.5V/0.4V
CE = V
CC
CE = V
IH
I
OUT
= 0mA, Duty = 100%, Cycle = 1µs at
V
CC
= 5.5V
I
OUT
= 0mA, Duty = 100%, Cycle = 150ns at
V
CC
= 5.5V
Input Voltage
RES_PIN
Output Voltage
I
OL
= 2.1 mA
I
OH
= -0.4 mA
1. I
LI
on RES = 100 uA max.
V
IL
V
IH
V
H
V
OL
V
OH
S
YMBOL
I
IL
I
LO
ICC1
ICC2
ICC3
M
IN
--
--
--
--
--
--
--
2.2
V
CC
-0.5
--
2.4
M
AX
2
1
2
20
1
15
50
0.8
--
--
0.4
--
V
V
U
NITS
µA
µA
µA
mA
mA
1000580
12.19.01 Rev 7
All data sheets are subject to change without notice
3
©2001 Maxwell Technologies
All rights reserved.
1 Megabit (128K x 8-Bit) EEPROM
28C011T
T
ABLE
7. 28C011T AC E
LECTRICAL
C
HARACTERISTICS FOR
R
EAD
O
PERATION 1
(V
CC
= 5V + 10%, T
A
= -55
TO
+125
°
C)
P
ARAMETER
Address Access Time
CE = OE = V
IL
, WE = V
IH
-120
-150
-200
Chip Enable Access Time
OE = V
IL
, WE = V
IH
-120
-150
-200
Output Enable Access Time
CE = V
IL
, WE = V
IH
-120
-150
-200
Output Hold to Address Change
CE = OE = V
IL
, WE = V
IH
-120
-150
-200
Output Disable to High-Z
2
CE = V
IL
, WE = V
IH
-120
-150
-200
CE = OE = V
IL
, WE = V
IH
-120
-150
-200
RES to Output Delay
3
CE = OE = V
IL
, WE = V
IH
-120
-150
-200
S
YMBOL
t
ACC
--
--
--
t
CE
--
--
--
t
OE
0
0
0
t
OH
0
0
0
t
DF
--
--
--
ns
0
0
0
0
0
0
50
50
60
300
350
450
ns
0
0
0
400
450
650
75
75
100
ns
120
150
200
ns
120
150
200
ns
M
IN
M
AX
U
NITS
ns
Memory
t
DFR
t
RR
1. Test conditions: Input pulse levels - 0.4V to 2.4V; input rise and fall times < 20ns; output load - 1 TTL gate + 100pF (including
scope and jig); reference levels for measuring timing - 0.8V/1.8V.
2. t
DF
and t
DFR
are defined as the time at which the output becomes an open circuit and data is no longer driven.
3. Guaranteed by design.
1000580
12.19.01 Rev 7
All data sheets are subject to change without notice
4
©2001 Maxwell Technologies
All rights reserved.
1 Megabit (128K x 8-Bit) EEPROM
28C011T
T
ABLE
8. 28C011T AC E
LECTRICAL
C
HARACTERISTICS FOR
B
YTE
E
RASE AND
B
YTE
W
RITE
O
PERATIONS
(V
CC
= 5V + 10%, T
A
= -55
TO
+125
°
C)
P
ARAMETER
Address Setup Time
-120
-150
-200
Chip Enable to Write Setup Time (WE controlled)
-120
-150
-200
Write Pulse Width
CE controlled
-120
-150
-200
WE controlled
-120
-150
-200
Address Hold Time
-120
-150
-200
Data Setup Time
-120
-150
-200
Data Hold Time
-120
-150
-200
Chip Enable Hold Time (WE controlled)
-120
-150
-200
Write Enable to Write Setup Time (CE controlled)
-120
-150
-200
Write Enable Hold Time (CE controlled)
-120
-150
-200
S
YMBOL
t
AS
M
IN1
0
0
0
0
0
0
M
AX
--
--
--
ns
--
--
--
ns
200
250
350
150
250
350
150
150
200
75
120
200
10
10
20
0
0
0
--
--
--
U
NITS
ns
t
CS
t
CW
t
WP
Memory
--
--
--
ns
--
--
--
ns
--
--
--
ns
--
--
--
--
--
--
ns
t
AH
t
DS
t
DH
t
CH
t
WS
0
0
0
t
WH
0
0
0
--
--
--
ns
ns
--
--
--
1000580
12.19.01 Rev 7
All data sheets are subject to change without notice
5
©2001 Maxwell Technologies
All rights reserved.
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