DATASHEET
GIGABIT ETHERNET CLOCK GENERATOR
Description
The IDT5T40166 is an ultra-low phase noise clock
generator that supports Gigabit Ethernet clock
requirements. It is used in PCs, embedded systems, and
high-end consumer applications to substantially increase
system performance. The device provides one differential
LVPECL clock at 125 MHz and one 25 MHz reference
clock.
IDT5T40166
Features
•
•
•
•
•
Packaged in 20-pin TSSOP
Supports Gigabit Ethernet applications
One differential LVPECL clock output for Gigabit Ethernet
Uses external 25 MHz clock or crystal input
Separate VDD pin for 25 MHz output clock to support
2.5 V operation
Block Diagram
VDD
VDD
25 MHz
crystal or
clock
X1
Oscillator
X2
Optional tuning
crystal capacitors
125M
125M
High
Performance
PLL Clock
Synthesizer
25M
GND
VDD25M
IDT®
GIGABIT ETHERNET CLOCK GENERATOR
1
IDT5T40166
REV A 082410
IDT5T40166
GIGABIT ETHERNET CLOCK GENERATOR
CLOCK SYNTHESIZER
Pin Assignment
GND
VDD
GND
XTAL/REFIN
XTALOUT
VDD
GND
VDD25M
25M
GND
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
VDD
GND
VDD
NC
GND
GND
VDD
VDD
125M
125M
20-pin (173 mil) TSSOP
Pin Descriptions
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Pin
Name
GND
VDD
GND
XTAL/REFIN
XTALOUT
VDD
GND
VDD25M
25M
GND
125M
125M
VDD
VDD
GND
GND
NC
VDD
GND
VDD
Pin
Type
Power
Power
Power
Input
—
Power
Power
Power
Power
Power
Output
Output
Power
Power
Power
Power
—
Power
Power
Power
Pin Description
Connect to ground.
Connect to +3.3 V supply.
Connect to ground.
Crystal connection. Connect to a fundamental mode crystal or clock input.
Crystal connection. Connect to a fundamental mode crystal or leave open.
Connect to +3.3 V supply.
Connect to ground.
Connect to +2.5 V supply. Supply for 25M clock.
25 MHz clock output.
Connect to ground.
125 MHz clock output. Differential LVPECL.
125 MHz clock output. Complementary differential LVPECL.
Connect to +3.3 V supply. Supply for 125M clock.
Connect to +3.3 V supply.
Connect to ground.
Connect to ground.
No connect. Internal test pin. Do not connect any signal on this pin.
Connect to +3.3 V supply.
Connect to ground.
Connect to +3.3 V supply.
IDT®
GIGABIT ETHERNET CLOCK GENERATOR
2
IDT5T40166
REV A 082410
IDT5T40166
GIGABIT ETHERNET CLOCK GENERATOR
CLOCK SYNTHESIZER
Application Information
Decoupling Capacitors
As with any high-performance mixed-signal IC, the
IDT5T40166 must be isolated from system power supply
noise to perform optimally.
Decoupling capacitors of 0.01 µF and 0.1 pF must be
connected between each VDD and the PCB ground plane.
External Components
A minimum number of external components are required for
proper operation. Decoupling capacitors of 0.01
μF
and 0.1
pF should be connected between VDD and GND as close to
the device as possible.
On chip capacitors-
Crystal capacitors is integrated to
support 8 pF crystal load. Crystal should be connected as
close to pins XTALIN and XTALOUT to optimize the initial
accuracy.
PCB Layout Recommendations
For optimum device performance and lowest output phase
noise, the following guidelines should be observed.
Each 0.01 µF and 0.1 pF decoupling capacitor should be
mounted on the component side of the board as close to the
VDD pin as possible. No vias should be used between
decoupling capacitor and VDD pin. The PCB trace to VDD
pin should be kept as short as possible, as should the PCB
trace to the ground via. Distance of the ferrite bead and bulk
decoupling from the device is less critical.
2) An optimum layout is one with all components on the
same side of the board, minimizing vias through other signal
layers (the ferrite bead and bulk decoupling capacitor can be
mounted on the back). Other signal traces should be routed
away from the IDT5T40166.
This includes signal traces just underneath the device, or on
layers adjacent to the ground plane layer used by the device.
LVPECL Test Condition
R
LOAD
= 50Ohm, C
LOAD
= 2pF
IDT®
GIGABIT ETHERNET CLOCK GENERATOR
3
IDT5T40166
REV A 082410
IDT5T40166
GIGABIT ETHERNET CLOCK GENERATOR
CLOCK SYNTHESIZER
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the IDT5T40166. These ratings are stress
ratings only. Functional operation of the device at these or any other conditions above those indicated in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for
extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended
operating temperature range.
Item
Supply Voltage, VDD, VDDA
All Inputs and Outputs
Ambient Operating Temperature (commercial)
Storage Temperature
Junction Temperature
Soldering Temperature
ESD Protection (Input)
5.5 V
Rating
-0.5 V to VDD+0.5 V
0 to +70° C
-65 to +150° C
125° C
260° C
2000 V min. (HBM)
DC Electrical Characteristics
Unless stated otherwise,
VDD = 3.3 V ±5%,
Ambient Temperature 0 to +70° C
Parameter
Supply Voltage
Operating Supply Current
Output Voltage Swing
Input Capacitance
Output Capacitance
Symbol
V
I
DD
V
SWING
C
IN
C
OUT
Conditions
Min.
3.135
Typ.
45
Max.
3.465
55
1.0
Units
V
mA
V
pF
pF
Pk-pk differential swing
Input pin capacitance
Output pin capacitance
0.5
3
5
1. VDD power ramp must be monotonous.
Unless stated otherwise,
VDD25 = 2.5 V ±5%,
Ambient Temperature 0 to +70° C
Parameter
Supply Voltage
Output High Voltage
1
Output Low Voltage
1
Operating Supply Current
Symbol
V
V
OH
V
OL
I
DD
Conditions
For 25M output
I
OH
= 8mA
I
OL
= 8mA
Min.
2.375
2.0
Typ.
Max.
2.625
0.4
Units
V
V
V
mA
8
15
IDT®
GIGABIT ETHERNET CLOCK GENERATOR
4
IDT5T40166
REV A 082410
IDT5T40166
GIGABIT ETHERNET CLOCK GENERATOR
CLOCK SYNTHESIZER
AC Electrical Characteristics
Unless stated otherwise,
VDD=3.3 V ±5%, VDD25M=2.5 V ±5%,
No Load, Ambient Temperature 0 to +70° C
Parameter
Input Frequency
Output Frequency
Jitter, pk-pk
1,2
Jitter, pk-pk
Jitter, LTJ
3
Jitter, LTJ
Rise Time
Fall Time
Rise Time
1,2
Fall Time
1,2
Duty
Cycle
1,2
PPM Error
Power-up Time
1
2
3
3
Symbol
Crystal Input
Conditions
LVPECL Output
LVTTL Output
Period pk-pk jitter for 125M clock
Period pk-pk jitter for 25M clock
Long term jitter for 125M clock
Long term jitter for 25M clock
Min.
Typ.
25
125
25
Max.
Units
MHz
MHz
MHz
60
100
125
100
400
400
500
500
45
55
0
5.0
10
ps
ps
ps
ps
ps
ps
ps
ps
%
ppm
ms
t
OR
t
OF
t
OR
t
OF
20-80% of VOH and VOL for 25M clock
20-80% of VOH and VOL for 25M clock
20-80% of VOH and VOL for 125M clock
20-80% of VOH and VOL for 125M clock
Frequency Synthesis Error (not due to
crystal CL)
t
STABLE
From power-up VDD = 3.3 V
Test setup is R
L
=50 ohms with 2 pF.
Measurement taken from a differential waveform.
1000
th
cycle jitter.
IDT®
GIGABIT ETHERNET CLOCK GENERATOR
5
IDT5T40166
REV A 082410
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