32-BIT FLOW-THRU
ERROR DETECTION
AND CORRECTION UNIT
Integrated Device Technology, Inc.
IDT49C465
IDT49C465A
FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
•
•
32-bit wide Flow-thruEDC unit, cascadable to 64 bits
Single-chip 64-bit Generate Mode
Separate system and memory buses
On-chip pipeline latch with external control
Supports bidirectional and common I/O memories
Corrects all single-bit errors
Detects all double-bit errors, some multiple-bit errors
Error Detection Time — 12ns
Error Correction Time — 14ns
On chip diagnostic registers.
Parity generation and checking on system data bus
Low power CMOS — 100mA typical at 20MH
Z
144-pin PGA and PQFP packages
Military product compliant to MIL-STD 883, Class B
™
DESCRIPTION
The IDT49C465/A is a 32-bit, two-data bus, Flow-thruEDC
unit. The chip provides single-error correction and two and
three bit error detection of both hard and soft memory errors.
It can be expanded to 64-bit widths by cascading 2 units,
without the need for additional external logic. The Flow-
thruEDC has been optimized for speed and simplicity of
control.
The EDC unit has been designed to be used in either of two
configurations in an error correcting memory system. The
bidirectional configuration is most appropriate for systems
using bidirectional memory buses. A second system
configuration utilizes external octal buffers, and is well suited
for systems using memory with separate I/O buses.
The IDT49C465/A supports partial word writes, pipelining
and error diagnostics. It also provides parity protection for
data on the system side.
SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM
MD
0–31
Correct
Logic
Memory
Checkbit
Generator
MD
Latch
MLE
Checkbit
Latch
Syndrome
Generator
Expansion
Logic
ERR
Detect
Logic
MERR
CBI
0–7
Mux
PCBI
0–7
SD
0–31
Pipeline
Latch
CONTROL
CONTROL
Byte
Mux
System
Checkbit
Generator
SD
Latch
SLE
PLE
Mux
CBO
0–7
2552 drw 01
CONTROL
CONTROL
The IDT logo is a registered trademark and Flow-thruEDC is a trademarkof Integrated Device Technology Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1995
Integrated Device Technology, Inc.
AUGUST 1995
DSC-9028/7
11.7
1
IDT49C465/A
32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATION
SD
2
SD
1
SD
0
PCBI
7
PCBI
6
PCBI
5
PCBI
4
PCBI
3
PCBI
2
PCBI
1
PCBI
0
CODE ID
1
CODE ID
0
GND
GND
MODE
1
MODE
0
V
CC
SD
5
SD
6
SD
7
SD
8
SD
9
SD
10
SD
11
GND
BE
1
SD
12
SD
13
SD
14
SD
15
SLE
PLE
SOE
GND
SD
16
SD
17
SD
18
SD
19
BE
2
SD
20
SD
21
SD
22
GND
SD
23
SD
24
SD
25
SD
26
SD
27
BE
3
SD
28
V
CC
V
CC
72
73
MERR
ERR
SYO
7
SYO
6
SY0
5
SY0
4
GND
SY0
3
SYO
2
SYO
1
SYO
0
MD
0
MD
1
MD
2
V
CC
V
CC
SD
4
BE
0
SD3
37
36
49C465Y
PQ144-2
108
109
SD
29
SD
30
SD
31
CBO
0
CBO
1
CBO
2
CBO
3
CBOE
CBO
4
CBO
5
CBO
6
CBO
7
PSEL
PERR
P
3
P
2
GND
GND
P
1
P
0
MODE 2
VCC
1
144
SYNCLK
SCLKEN
CLEAR
CBI
0
CBI
1
CBI
2
CBI
3
GND
CBI
4
CBI
5
CBI
6
CBI
7
MD
31
V
CC
V
CC
V
CC
MD
3
MD
4
MD
5
MD
6
MD
7
MD
8
MD
9
GND
MD
10
MD
11
MD
12
MD
13
MD
14
MD
15
MLE
MOE
GND
MD
16
MD
17
MD
18
MD
19
MD
20
MD
21
MD
22
MD
23
GND
MD
24
MD
25
MD
26
MD
27
MD
28
MD
29
MD
30
V
CC
2552 drw 02
PQFP
TOP VIEW
11.7
2
IDT49C465/A
32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATION
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
V
CC
CODE CODE MODE
SD
2
PCBI
6
PCBI
5
PCBI
3
ID
1
MERR ERR SYO
5
SYO
3
SYO
1
MD
1
1
ID
0
SD
1
PCBI
7
PCBI
4
PCBI
1
PCBI
0
MODE SYO
6
SYO
4
SYO
2
MD
0
MD
2
0
V
CC
MD
5
SD
6
SD
4
SD
9
SD
5
V
CC
BE
0
V
CC
SD
3
SD 0 PCBI
2
GND
GND SYO
7
GND SYO
0
V
CC
MD
3
MD
4
MD
6
MD
9
MD
8
GND
SD
11
SD
7
SD
12
SD
10
SD
8
SD
15
SLE
SOE
BE
1
GND
MD
7
MD
10
MD
11
MD
12
MD
13
MD
15
MOE MD
14
MLE
G144-2
GND MD
17
MD
16
MD
20
MD
21
MD
18
GND MD
23
MD
19
MD
27
MD
25
MD
22
NC*
V
CC
CB0
0
CBOE CB0
7
GND GND
P
3
P
2
H
V
CC
MD
28
MD
24
SD
13
SD
14
PLE
GND
SD
17
SD
19
SD
16
SD
18
BE
2
SD
20
SD
21
SD
22
SD
25
GND SD
24
BE
3
SD
23
SD
26
SD
28
SD
27
V
CC
A
V
CC
SD
29
SD
31
CB0
2
CB0
4
CB0
6
SD
30
CB0
1
CB0
3
CB0
5
PSEL PERR
B
C
D
E
F
G
SCLK
GND CB1
6
CB1
7
MD
30
MD
26
EN
MODE SYN-
2
CLK CB1
0
CB1
3
CB1
4
MD
31
MD
29
P
1
J
P
0
K
CLEAR
CB1
1
CB1
2
CB1
5
V
CC
L
M
N
P
R
2552 drw 03
*Tied to Vcc internally
PGA (CAVITY UP)
TOP VIEW
11.7
3
Dashed Line = Diagnostic path
8
8
8
8
8
8
ERR
MERR
PCBI
0–7
MUX
8
ERROR
DETECT
INTERNAL
FINAL
SYNDRO
ME
MUX
CHECK
BIT
LATCH
8
SYNDROME
GENERATOR
MUX
CBI
0–7
8
SYO
0–7
8
MUX
PLE
8
MD
CHECKBIT
GENERATOR
MD
LATCH
MLE
SOE
ERROR
CORRECT
MUX
ERROR DATA LATCH
CLEAR
BE
0–3
4
1 OF 4
BYTES
DIAGNOSTIC
LATCHES
BYTE MUX
PIPE
LATCH
MD
0–31
INTERNAL SYNCLK
IDT49C465/A
32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT
DETAILED FUNCTIONAL BLOCK DIAGRAM
SD
0–31
11.7
SD
LATCH
BE
0–3
4
MOE
SLE
PSEL
8
4
MUX
P
0–3
4
PARITY
GEN
SD
CHECKBIT
GENERATOR
8
8
CBO
0–7
CBOE
4
PARITY
CHECK
MUX
8
PERR
SD
CHECKBIT
GENERATOR
/ERR
INTERNAL SYNCLK
8
PCBI
0–7
SYNCLK
SCLKEN
CLEAR
2
CODE ID
0,1
MODE
0–2
3
CONTROL
LOGIC
2552 drw 04
MILITARY AND COMMERCIAL TEMPERATURE RANGES
4
IDT49C465/A
32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SYSTEM CONFIGURATIONS
The IDT49C465 EDC unit can be used in various
configurations in an EDC system. The basic configurations
are shown below.
Figure 1 illustrates a bidirectional configuration, which is
most appropriate for systems using bidirectional memory
buses. It is the simplest configuration to understand and use.
During a correction cycle, the corrected data word can be
simultaneously output on both the system bus and memory
bus. Logically, no other parts are required for the correction
function. During partial-word-write operations, the new bytes
are internally combined with the corrected old bytes for
checkbit generation and writing to memory.
Figure 3 illustrates a third configuration which utilizes
external buffers and is also well suited for systems using
memory with separate I/O buses. Since data from memory
does not need to pass through the part on every cycle, the
EDC system may operate in “bus-watch” mode. As in the
separate I/O configuration, corrected data is output on the SD
outputs.
MEMORY
INPUT BUS
CHECKBIT
I/O
MEMORY
OUTPUT BUS
CBO
SD
EDC
CBI
MD
CPU
I/O
SD
EDC
MD
MEMORY
I/O
EXT. BUFFER
EXT.BUFFER
EXT. BUFFER
CPU BUS
2552 drw 07
CBI
CHECKBITS
CBO
2552 drw 05
Figure 1. Common I/O Configuration
Figure 3. Bypassed Separate I/O Configuration
Figure 2 illustrates a separate I/O configuration. This is
appropriate for systems using separate I/O memory buses.
This configuration allows separate input and output memory
buses to be used. Corrected data is output on the SD outputs
for the system and for re-write to memory. Partial word-write
bytes are combined externally for writing and checkbit
generation.
CPU
Figure 4 illustrates the single-chip generate-only mode for
very fast 64-bit checkbit generation in systems that use
separate checkbit-generate and detect-correct units. If this is
not desired, 64-bit checkbit generation and correction can be
done with just 2 EDC units. 64-bit correction is also straight-
forward, fast and requires no extra hardware for the
expansion.
CHECK
BITS OUT
CHECK
BITS IN
MEMORY
INPUT BUS
EXT. BUFFER
MEMORY
INPUTS
MEMORY
OUTPUT BUS
MEMORY
INPUT BUS
CBO
64-BIT
GEN.
ONLY
CBI
LOWER
DATA
EDC
BUFFER
BUFFER
UPPER
DATA
EDC
BUFFER
SD
MD
EDC
CBI
CHECKBITS
CBO
2552 drw 06
MEMORY
OUTPUTS
BUFFER
EDC
CPU BUS
2552 drw 08
Figure 2. Separate I/O Configuration
Figure 4. Separate Generate/Correction Units
with 64-Bit Checkbit Generation
11.7
5
Microchip MCU
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
