®
FAST CMOS
OCTAL REGISTERED
TRANSCEIVERS
DESCRIPTION:
IDT29FCT52A/B/C
IDT29FCT53A/B/C
Integrated Device Technology, Inc.
FEATURES:
• Equivalent to AMD’s Am2952/53 and National’s
29F52/53 in pinout/function
• IDT29FCT52A/53A equivalent to FAST™ speed
•
IDT29FCT52B/53B 25% faster than FAST
•
IDT29FCT52C/53C 37% faster than FAST
• I
OL
= 64mA (commercial) and 48mA (military)
• I
IH
and I
IL
only 5µA max.
• CMOS power levels (2.5mW typ. static)
• TTL input and output level compatible
• CMOS output level compatible
• Available in 24-pin DIP, SOIC, 28-pin LCC with JEDEC
standard pinout
• Product available in Radiation Tolerant and Radiation
Enhanced versions
• Military product compliant to MIL-STD-883, Class B
The IDT29FCT52A/B/C and IDT29FCT53A/B/C are 8-bit
registered transceivers manufactured using an advanced
dual metal CMOS technology. Two 8-bit back-to-back regis-
ters store data flowing in both directions between two bidirec-
tional buses. Separate clock, clock enable and 3-state output
enable signals are provided for each register. Both A outputs
and B outputs are guaranteed to sink 64mA.
The IDT29FCT52A/B/C is a non-inverting option of the
IDT29FCT53A/B/C.
FUNCTIONAL BLOCK DIAGRAM
(1)
CPA
CEA
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
D
0
CE CP Q
0
D
1
D
2
Q
1
Q
2
OEB
B
0
B
1
B
2
B
3
B
4
B
5
B
6
B
7
D
3
Q
3
A
D
4
Reg. Q
4
D
5
D
6
D
7
Q
5
Q
6
Q
7
Q
0
Q
1
Q
2
Q
3
Q
4
Q
5
D
0
D
1
D
2
D
3
B
Reg. D
4
D
5
Q
6
D
6
Q
7
CE CP D
7
OEA
NOTE:
1. IDT29FCT52 function is shown.
CPB
CEB
2533 drw 01
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
FAST is a trademark of National Semiconductor Co.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1992
Integrated Device Technology, Inc.
MAY 1992
DSC-4605/3
7.1
1
IDT29FCT52A/B/C, IDT29FCT53A/B/C
FAST CMOS OCTAL REGISTERED TRANSCEIVERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
INDEX
B
7
B
6
B
5
B
4
B
3
B
2
B
1
B
0
OEB
CPA
CEA
GND
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
P24-1,
D24-1,
E24-1
&
SO24-2
21
20
19
18
17
16
15
14
13
DIP/CERPACK/SOIC
TOP VIEW
CPA
CEA
GND
NC
CEB
CPB
OEA
LCC
TOP VIEW
Vcc
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
OEA
CPB
CEB
B
5
B
6
B
7
NC
Vcc
A
7
A
6
4
3
2
1
28 27 26
25
24
23
5
6
7
8
9
10
11
12 13 14 15 16 17 18
B
4
B
3
B
2
NC
B
1
B
0
OEB
L28-1
22
21
20
19
A
5
A
4
A
3
NC
A
2
A
1
A
0
2533 drw 02
PIN DESCRIPTION
Name
A
0-7
B
0-7
CPA
I/O
I/O
I/O
I
I
Description
Eight bidirectional lines carrying the A Register inputs or B Register outputs.
Eight bidirectional lines carrying the B Register inputs or A Register outputs.
Clock for the A Register. When
CEA
is LOW, data is entered into the A Register on the LOW-to-HIGH transition
of the CPA signal.
Clock Enable for the A Register. When
CEA
is LOW, data is entered into the A Register on the LOW-to-HIGH
transition of the CPA signal. When
CEA
is HIGH, the A Register holds its contents, regardless of CPA signal
transitions.
Output Enable for the A Register. When
OEB
is LOW, the A Register outputs are enabled onto the B
0-7
lines. When
OEB
is HIGH, the B
0-7
outputs are in the high-impedance state.
CEA
OEB
CPB
I
I
I
Clock for the B Register. When
CEB
is LOW, data is entered into the B Register on the LOW-to-HIGH transition
of the CPB signal.
Clock Enable for the B Register. When
CEB
is LOW, data is entered into the B Register on the LOW-to-HIGH
transition of the CPB signal. When
CEB
is HIGH, the B Register holds its contents, regardless of CPB signal
transitions.
Output Enable for the B Register. When
OEA
is LOW, the B Register outputs are enabled onto the A
0-7
lines. When
OEA
is HIGH, the A
0-7
outputs are in the high-impedance state.
2533 tbl 01
CEB
OEA
I
REGISTER FUNCTION TABLE
(1)
(Applies to A or B Register)
D
X
L
H
Inputs
CP
X
↑
↑
OUTPUT CONTROL
(1)
Internal
Y-Outputs
52
Z
L
H
53
Z
H
L
2533 tbl 03
CE
H
L
L
Internal
Q
NC
L
H
Function
Hold Data
Load Data
2533 tbl 02
OE
H
L
L
Q
X
L
H
Function
Disable Outputs
Enable Outputs
NOTE:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
NC = No Change
↑
= LOW-to-HIGH Transition
7.1
2
IDT29FCT52A/B/C, IDT29FCT53A/B/C
FAST CMOS OCTAL REGISTERED TRANSCEIVERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
Rating
Commercial
–0.5 to +7.0
Military
–0.5 to +7.0
Unit
V
V
TERM(2)
Terminal Voltage
with Respect
to GND
(3)
V
TERM
Terminal Voltage
with Respect
to GND
T
A
Operating
Temperature
T
BIAS
Temperature
Under Bias
T
STG
Storage
Temperature
P
T
Power Dissipation
DC Output Current
I
OUT
CAPACITANCE
(T
A
= +25°C, f = 1.0MHz)
Symbol
C
IN
C
I/O
Parameter
(1)
Input
Capacitance
I/O
Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
Typ.
6
8
Max.
10
12
Unit
pF
pF
–0.5 to V
CC
–0.5 to V
CC
V
0 to +70
–55 to +125
–55 to +125
0.5
120
–55 to +125
–65 to +135
–65 to +150
0.5
120
°C
°C
°C
W
mA
NOTE:
2533 tbl 05
1. This parameter is guaranteed by characterization data and not tested.
NOTES:
2533 tbl 04
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability. No terminal voltage
may exceed +0.5V unless otherwise noted.
2. Inputs and V
CC
terminals only.
3. Outputs and I/O terminals only.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: V
LC
= 0.2V; V
HC
= V
CC
– 0.2V
Commercial: T
A
= 0°C to +70°C, V
CC
= 5.0V
±
5%; Military: T
A
= –55°C to +125°C, V
CC
= 5.0V
±
10%
Symbol
V
IH
V
IL
I
IH
I
IL
I
IH
I
IL
V
IK
I
OS
V
OH
Parameter
Input HIGH Level
Input LOW Level
Input HIGH Current
(Except I/O Pins)
Input LOW Current
(Except I/O Pins)
Input HIGH Current
(I/O Pins Only)
Input LOW Current
(I/O Pins Only)
Clamp Diode Voltage
Short Circuit Current
Output HIGH Voltage
Vcc = Min., I
N
= –18mA
Vcc = Max.
(3)
, V
O
= GND
Vcc = 3V, V
IN
= V
LC
or V
HC
, I
OH
= –32µA
Vcc = Min.
V
IN
= V
IH
or V
IL
V
OL
Output LOW Voltage
I
OH
= –300µA
I
OH
= –15mA MIL.
I
OH
= –24mA COM’L.
Vcc = 3V, V
IN
= V
LC
or V
HC
, I
OL
= 300µA
Vcc = Min.
V
IN
= V
IH
or V
IL
I
OL
= 300µA
I
OL
= 48mA MIL.
(5)
I
OL
= 64mA COM’L.
(5)
V
CC
= Max.
Test Conditions
(1)
Guaranteed Logic HIGH Level
Guaranteed Logic LOW Level
V
CC
= Max.
V
I
=V
CC
V
I
= 2.7V
V
I
= 0.5V
V
I
= GND
V
I
= V
CC
V
I
= 2.7V
V
I
= 0.5V
V
I
= GND
Min.
2.0
—
—
—
—
—
—
—
—
—
—
–60
V
HC
V
HC
2.4
2.4
—
—
—
—
Typ.
(2)
—
—
—
—
—
—
—
—
—
—
–0.7
–120
V
CC
V
CC
4.0
4.0
GND
GND
0.3
0.3
Max.
—
0.8
5
5
(4)
Unit
V
V
µA
–5
(4)
–5
15
15
(4)
–15
(4)
–15
–1.2
—
—
—
—
—
V
LC
V
LC(4)
0.55
0.55
V
V
mA
V
µA
NOTES:
2533 tbl 06
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. This parameter is guaranteed but not tested.
5. These are maximum I
OL
values per output, for 8 outputs turned on simultaneously. Total maximum I
OL
(all outputs) is 512mA for commercial and
384mA for military. Derate I
OL
for number of outputs exceeding 8 turned on simultaneously.
7.1
3
IDT29FCT52A/B/C, IDT29FCT53A/B/C
FAST CMOS OCTAL REGISTERED TRANSCEIVERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
V
LC
= 0.2V; V
HC
= V
CC
– 0.2V
Symbol
I
CC
∆I
CC
I
CCD
Parameter
Quiescent Power Supply
Current
Quiescent Power Supply
Current TTL Inputs HIGH
Dynamic Power Supply
Current
(4)
Test Conditions
(1)
V
CC
= Max.
V
IN
≥
V
HC
; V
IN
≤
V
LC
Vcc = Max.
V
IN
= 3.4V
(3)
Vcc = Max.
Outputs Open
OEA
or
OEB
= GND
One Input Toggling
50% Duty Cycle
Vcc = Max.
Outputs Open
f
CP
= 10MHz
50% Duty Cycle
OEA
or
OEB
= GND
One Bit Toggling
at fi = 5MHz
50% Duty Cycle
V
CC
= Max.
Outputs Open
f
CP
= 10MHz
50% Duty Cycle
OEA
or
OEB
= GND
Eight Bits Toggling
at f
i
= 2.5MHz
50% Duty Cycle
V
IN
≥
V
HC
V
IN
≤
V
LC
Min.
—
—
—
Typ.
(2)
0.5
0.5
0.15
Max.
1.5
2.0
0.25
Unit
µA
mA
mA/
MHz
I
C
Total Power Supply
Current
(6)
V
IN
≥
V
HC
V
IN
≤
V
LC
(FCT)
—
2.0
4.0
mA
V
IN
= 3.4V
V
IN
= GND
V
IN
≥
V
HC
V
IN
≤
V
LC
(FCT)
—
2.5
6.0
—
4.3
7.8
(5)
V
IN
= 3.4V
V
IN
= GND
—
6.5
16.8
(5)
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 5.0V, +25°C ambient.
3. Per TTL driven input (V
IN
= 3.4V); all other inputs at V
CC
or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
5. Values for these conditions are examples of the I
CC
formula. These limits are guaranteed but not tested.
6. I
C
= I
QUIESCENT
+ I
INPUTS
+ I
DYNAMIC
I
C
= I
CC
+
∆I
CC
D
H
N
T
+ I
CCD
(f
CP
/2 + f
i
N
i
)
I
CC
= Quiescent Current
∆I
CC
= Power Supply Current for a TTL High Input (V
IN
= 3.4V)
D
H
= Duty Cycle for TTL Inputs High
N
T
= Number of TTL Inputs at D
H
I
CCD
= Dynamic Current Caused by an Output Transition Pair (HLH or LHL)
f
CP
= Clock Frequency for Register Devices (Zero for Non-Register Devices)
f
i
= Input Frequency
N
i
= Number of Inputs at f
i
All currents are in milliamps and all frequencies are in megahertz.
2533 tbl 07
7.1
4
IDT29FCT52A/B/C, IDT29FCT53A/B/C
FAST CMOS OCTAL REGISTERED TRANSCEIVERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
IDT29FCT52A/53A
Com’l.
Symbol
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
SU
Parameter
Propagation Delay
CPA, CPB to A
n
, B
n
Output Enable Time
OEA
or
OEB
to
A
n
or B
n
Output Disable Time
OEA
or
OEB
to
A
n
or B
n
Set-up Time HIGH
or LOW A
n
, B
n
to
CPA, CPB
Hold Time HIGH
or LOW A
n
, B
n
to
CPA, CPB
Set-up Time HIGH
or
LOW
CEA
,
CEB
to
CPA, CPB
Hold Time HIGH
or LOW
CEA
,
CEB
to
CPA, CPB
Pulse Width, HIGH
(3)
or LOW CPA or CPB
C
L
= 50pF
R
L
= 500Ω
2.0
1.5
10.0
10.5
Mil.
2.0
1.5
11.0
13.0
IDT29FCT52B/53B
Com’l.
2.0
1.5
7.5
8.0
2.0
1.5
Mil.
8.0
8.5
IDT29FCT52C/53C
Com’l.
2.0
1.5
6.3
7.0
Mil.
2.0
1.5
7.3
8.0
ns
ns
Condition
(1)
Min.
(2)
Max. Min.
(2)
Max. Min.
(2)
Max. Min.
(2)
Max. Min.
(2)
Max. Min
.
(2)
Max.
Unit
1.5
10.0
1.5
10.0
1.5
7.5
1.5
8.0
1.5
6.5
1.5
7.5
ns
2.5
—
2.5
—
2.5
—
2.5
—
2.5
—
2.5
—
ns
t
H
2.0
—
2.0
—
1.5
—
1.5
—
1.5
—
1.5
—
ns
t
SU
3.0
—
3.0
—
3.0
—
3.0
—
3.0
—
3.0
—
ns
t
H
2.0
—
2.0
—
2.0
—
2.0
—
2.0
—
2.0
—
ns
t
W
3.0
—
3.0
—
3.0
—
3.0
—
3.0
—
3.0
—
ns
2533 tbl 08
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. This parameter is guaranteed but not tested.
7.1
5
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