82C54
March 1997
CMOS Programmable Interval Timer
Description
The Intersil 82C54 is a high performance CMOS Program-
mable Interval Timer manufactured using an advanced 2
micron CMOS process.
The 82C54 has three independently programmable and
functional 16-bit counters, each capable of handling clock
input frequencies of up to 8MHz (82C54) or 10MHz
(82C54-10) or 12MHz (82C54-12).
The high speed and industry standard configuration of the
82C54 make it compatible with the Intersil 80C86, 80C88,
and 80C286 CMOS microprocessors along with many other
industry standard processors. Six programmable timer
modes allow the 82C54 to be used as an event counter,
elapsed time indicator, programmable one-shot, and many
other applications. Static CMOS circuit design insures low
power operation.
The Intersil advanced CMOS process results in a significant
reduction in power with performance equal to or greater than
existing equivalent products.
Features
• 8MHz to 12MHz Clock Input Frequency
• Compatible with NMOS 8254
- Enhanced Version of NMOS 8253
• Three Independent 16-Bit Counters
• Six Programmable Counter Modes
• Status Read Back Command
• Binary or BCD Counting
• Fully TTL Compatible
• Single 5V Power Supply
• Low Power
- ICCSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10µA
- ICCOP . . . . . . . . . . . . . . . . . . . . . . . . . . 10mA at 8MHz
• Operating Temperature Ranges
- C82C54 . . . . . . . . . . . . . . . . . . . . . . . . . .0
o
C to +70
o
C
- I82C54 . . . . . . . . . . . . . . . . . . . . . . . . . -40
o
C to +85
o
C
- M82C54 . . . . . . . . . . . . . . . . . . . . . . . -55
o
C to +125
o
C
Pinouts
82C54 (PDIP, CERDIP, SOIC)
TOP VIEW
D7 1
D6 2
D5 3
D4 4
D3 5
D2 6
D1 7
D0 8
CLK 0 9
OUT 0 10
GATE 0 11
GND 12
24 VCC
23 WR
22 RD
21 CS
20 A1
19 A0
18 CLK 2
17 OUT 2
16 GATE 2
15 CLK 1
14 GATE 1
13 OUT 1
12
OUT 0
13
GATE 0
14
GND
15
NC
16
OUT 1
17
GATE 1
18
CLK 1
NC 11
19 GATE 2
D4
D3
D2
D1
D0
5
6
7
8
9
25 NC
24 CS
23 A1
22 A0
21 CLK2
20 OUT 2
82C54 (PLCC/CLCC)
TOP VIEW
VCC
WR
27
D5
D6
D7
NC
RD
26
4
3
2
1
28
CLK 0 10
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
|
Copyright
©
Intersil Corporation 1999
File Number
2970.1
4-1
82C54
Ordering Information
PART NUMBERS
8MHz
CP82C54
IP82C54
CS82C54
IS82C54
CD82C54
ID82C54
MD82C54/B
MR82C54/B
SMD # 8406501JA
SMD# 84065013A
CM82C54
10MHz
CP82C54-10
IP82C54-10
CS82C54-10
IS82C54-10
CD82C54-10
ID82C54-10
MD82C54-10/B
MR82C54-10/B
-
-
CM82C54-10
12MHz
CP82C54-12
IP82C54-12
CS82C54-12
IS82C54-12
CD82C54-12
ID82C54-12
MD82C54-12/B
MR82C54-12/B
8406502JA
84065023A
CM82C54-12
TEMPERATURE
RANGE
0
o
C to +70
o
C
-40
o
C to +85
o
C
0
o
C to +70
o
C
-40
o
C to +85
o
C
0
o
C to +70
o
C
-40
o
C to +85
o
C
-55
o
C to +125
o
C
-55
o
C to +125
o
C
-55
o
C to +125
o
C
-55
o
C to +125
o
C
0
o
C to +70
o
C
PACKAGE
24 Lead PDIP
24 Lead PDIP
28 Lead PLCC
28 Lead PLCC
24 Lead CERDIP
24 Lead CERDIP
24 Lead CERDIP
28 Lead CLCC
24 Lead CERDIP
28 Lead CLCC
24 Lead SOIC
PKG. NO.
E24.6
E24.6
N28.45
N28.45
F24.6
F24.6
F24.6
J28.A
F24.6
J28.A
M24.3
Functional Diagram
DATA/
BUS
BUFFER
CLK 0
COUNTER
0
GATE 0
OUT 0
CONTROL
WORD
REGISTER
RD
WR
A
0
A
1
CS
CLK 2
CONTROL
WORD
REGISTER
COUNTER
2
GATE 2
OUT 2
GATE n
CLK n
OUT n
COUNTER INTERNAL BLOCK DIAGRAM
READ/
WRITE
LOGIC
INTERNAL BUS
COUNTER
1
CLK 1
GATE 1
OUT 1
CONTROL
LOGIC
CE
STATUS
LATCH
CR
M
STATUS
REGISTER
CR
L
INTERNAL BUS
D
7
- D
0
8
OL
M
OL
L
Pin Description
SYMBOL
D7 - D0
CLK 0
OUT 0
GATE 0
GND
OUT 1
GATE 1
CLK 1
GATE 2
OUT 2
DIP PIN
NUMBER
1-8
9
10
11
12
13
14
15
16
17
O
I
I
I
O
TYPE
I/O
I
O
I
DEFINITION
DATA: Bi-directional three-state data bus lines, connected to system data bus.
CLOCK 0: Clock input of Counter 0.
OUT 0: Output of Counter 0.
GATE 0: Gate input of Counter 0.
GROUND: Power supply connection.
OUT 1: Output of Counter 1.
GATE 1: Gate input of Counter 1.
CLOCK 1: Clock input of Counter 1.
GATE 2: Gate input of Counter 2.
OUT 2: Output of Counter 2.
4-2
82C54
Pin Description
SYMBOL
CLK 2
A0, A1
DIP PIN
NUMBER
18
19 - 20
(Continued)
TYPE
I
I
CLOCK 2: Clock input of Counter 2.
ADDRESS: Select inputs for one of the three counters or Control Word Register for read/write
operations. Normally connected to the system address bus.
A1
0
0
1
1
CS
RD
WR
V
CC
21
22
23
24
I
I
I
A0
0
1
0
1
SELECTS
Counter 0
Counter 1
Counter 2
Control Word Register
DEFINITION
CHIP SELECT: A low on this input enables the 82C54 to respond to RD and WR signals. RD and
WR are ignored otherwise.
READ: This input is low during CPU read operations.
WRITE: This input is low during CPU write operations.
V
CC
: The +5V power supply pin. A 0.1µF capacitor between pins VCC and GND is recommended
for decoupling.
Functional Description
General
The 82C54 is a programmable interval timer/counter
designed for use with microcomputer systems. It is a general
purpose, multi-timing element that can be treated as an
array of I/O ports in the system software.
The 82C54 solves one of the most common problems in any
microcomputer system, the generation of accurate time
delays under software control. Instead of setting up timing
loops in software, the programmer configures the 82C54 to
match his requirements and programs one of the counters
for the desired delay. After the desired delay, the 82C54 will
interrupt the CPU. Software overhead is minimal and vari-
able length delays can easily be accommodated.
Some of the other computer/timer functions common to micro-
computers which can be implemented with the 82C54 are:
• Real time clock
• Event counter
• Digital one-shot
• Programmable rate generator
• Square wave generator
• Binary rate multiplier
• Complex waveform generator
• Complex motor controller
Data Bus Buffer
This three-state, bi-directional, 8-bit buffer is used to inter-
face the 82C54 to the system bus (see Figure 1).
FIGURE 1. DATA BUS BUFFER AND READ/WRITE LOGIC
FUNCTIONS
CONTROL
WORD
REGISTER
COUNTER
2
D
7
- D
0
DATA/
BUS
BUFFER
CLK 0
COUNTER
0
GATE 0
OUT 0
8
RD
WR
A
0
A
1
CS
READ/
WRITE
LOGIC
INTERNAL BUS
COUNTER
1
CLK 1
GATE 1
OUT 1
CLK 2
GATE 2
OUT 2
Read/Write Logic
The Read/Write Logic accepts inputs from the system bus and
generates control signals for the other functional blocks of the
82C54. A1 and A0 select one of the three counters or the Con-
trol Word Register to be read from/written into. A “low” on the
RD input tells the 82C54 that the CPU is reading one of the
counters. A “low” on the WR input tells the 82C54 that the CPU
is writing either a Control Word or an initial count. Both RD and
WR are qualified by CS; RD and WR are ignored unless the
82C54 has been selected by holding CS low.
4-3
82C54
Control Word Register
The Control Word Register (Figure 2) is selected by the
Read/Write Logic when A1, A0 = 11. If the CPU then does a
write operation to the 82C54, the data is stored in the Con-
trol Word Register and is interpreted as a Control Word used
to define the Counter operation.
The Control Word Register can only be written to; status
information is available with the Read-Back Command.
INTERNAL BUS
CONTROL
WORD
REGISTER
STATUS
LATCH
CR
M
STATUS
REGISTER
CR
L
D
7
- D
0
8
DATA/
BUS
BUFFER
CLK 0
COUNTER
0
GATE 0
OUT 0
CONTROL
LOGIC
CE
OL
M
OL
L
RD
WR
A
0
A
1
CS
READ/
WRITE
LOGIC
INTERNAL BUS
COUNTER
1
CLK 1
GATE 1
OUT 1
GATE n
CLK n
OUT n
FIGURE 3. COUNTER INTERNAL BLOCK DIAGRAM
CLK 2
CONTROL
WORD
REGISTER
COUNTER
2
GATE 2
OUT 2
FIGURE 2. CONTROL WORD REGISTER AND COUNTER
FUNCTIONS
OLM and OLL are two 8-bit latches. OL stands for “Output
Latch”; the subscripts M and L for “Most significant byte” and
“Least significant byte”, respectively. Both are normally referred
to as one unit and called just OL. These latches normally “fol-
low” the CE, but if a suitable Counter Latch Command is sent to
the 82C54, the latches “latch” the present count until read by
the CPU and then return to “following” the CE. One latch at a
time is enabled by the counter’s Control Logic to drive the inter-
nal bus. This is how the 16-bit Counter communicates over the
8-bit internal bus. Note that the CE itself cannot be read; when-
ever you read the count, it is the OL that is being read.
Similarly, there are two 8-bit registers called CRM and CRL (for
“Count Register”). Both are normally referred to as one unit and
called just CR. When a new count is written to the Counter, the
count is stored in the CR and later transferred to the CE. The
Control Logic allows one register at a time to be loaded from
the internal bus. Both bytes are transferred to the CE simulta-
neously. CRM and CRL are cleared when the Counter is pro-
grammed for one byte counts (either most significant byte only
or least significant byte only) the other byte will be zero. Note
that the CE cannot be written into; whenever a count is written,
it is written into the CR.
The Control Logic is also shown in the diagram. CLK n,
GATE n, and OUT n are all connected to the outside world
through the Control Logic.
82C54 System Interface
The 82C54 is treated by the system software as an array of
peripheral I/O ports; three are counters and the fourth is a
control register for MODE programming.
Basically, the select inputs A0, A1 connect to the A0, A1
address bus signals of the CPU. The CS can be derived
directly from the address bus using a linear select method or
it can be connected to the output of a decoder.
Counter 0, Counter 1, Counter 2
These three functional blocks are identical in operation, so
only a single Counter will be described. The internal block
diagram of a signal counter is shown in Figure 3. The
counters are fully independent. Each Counter may operate
in a different Mode.
The Control Word Register is shown in the figure; it is not
part of the Counter itself, but its contents determine how the
Counter operates.
The status register, shown in the figure, when latched, con-
tains the current contents of the Control Word Register and
status of the output and null count flag. (See detailed expla-
nation of the Read-Back command.)
The actual counter is labeled CE (for Counting Element). It is
a 16-bit presettable synchronous down counter.
4-4
82C54
Operational Description
General
After power-up, the state of the 82C54 is undefined. The
Mode, count value, and output of all Counters are undefined.
How each Counter operates is determined when it is pro-
grammed. Each Counter must be programmed before it can
be used. Unused counters need not be programmed.
Programming the 82C54
Counters are programmed by writing a Control Word and
then an initial count.
All Control Words are written into the Control Word Register,
which is selected when A1, A0 = 11. The Control Word spec-
ifies which Counter is being programmed.
By contrast, initial counts are written into the Counters, not
the Control Word Register. The A1, A0 inputs are used to
select the Counter to be written into. The format of the initial
count is determined by the Control Word used.
ADDRESS BUS (16)
A1
A0
CONTROL BUS
I/OR I/OW
DATA BUS (8)
8
A1
A0
CS
D0 - D7
82C54
COUNTER
1
OUT GATE CLK
RD
WR
SC - Select Counter
SC1
0
0
1
1
SC0
0
1
0
1
Select Counter 0
Select Counter 1
Select Counter 2
Read-Back Command (See Read Operations)
RW - Read/Write
RW1 RW0
0
0
1
1
0
1
0
1
Counter Latch Command (See Read Operations)
Read/Write least significant byte only.
Read/Write most significant byte only.
Read/Write least significant byte first, then most
significant byte.
M - Mode
M2
0
0
X
X
1
1
M1
0
0
1
1
0
0
M0
0
1
0
1
0
1
Mode 0
Mode 1
Mode 2
Mode 3
Mode 4
Mode 5
BCD - Binary Coded Decimal
0
Binary Counter 16-bit
Binary Coded Decimal (BCD) Counter (4 Decades)
COUNTER
0
OUT GATE CLK
COUNTER
2
OUT GATE CLK
1
NOTE: Don’t Care bits (X) should be 0 to insure compatibility with
future products.
Possible Programming Sequence
FIGURE 4. 82C54 SYSTEM INTERFACE
Write Operations
The programming procedure for the 82C54 is very flexible.
Only two conventions need to be remembered:
1. For Each Counter, the Control Word must be written
before the initial count is written.
2. The initial count must follow the count format specified in the
Control Word (least significant byte only, most significant byte
only, or least significant byte and then most significant byte).
Since the Control Word Register and the three Counters have
separate addresses (selected by the A1, A0 inputs), and each
Control Word specifies the Counter it applies to (SC0, SC1 bits),
no special instruction sequence is required. Any programming
sequence that follows the conventions above is acceptable.
Control Word Format
A1, A0 = 11; CS = 0; RD = 1; WR = 0
D7
SC1
D6
SC0
D5
RW1
D4
RW0
D3
M2
D2
M1
D1
M0
D0
BCD
A1
Control Word - Counter 0
LSB of Count - Counter 0
MSB of Count - Counter 0
Control Word - Counter 1
LSB of Count - Counter 1
MSB of Count - Counter 1
Control Word - Counter 2
LSB of Count - Counter 2
MSB of Count - Counter 2
1
0
0
1
0
0
1
1
1
A0
1
0
0
1
1
1
1
0
0
Possible Programming Sequence
A1
Control Word - Counter 0
Control Word - Counter 1
Control Word - Counter 2
LSB of Count - Counter 2
1
1
1
1
A0
1
1
1
0
4-5
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