3.3 VOLT Time Slot Interchange
Digital Switch
2,048 x 2,048
FEATURES:
♦
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♦
♦
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PRELIMINARY
IDT72V70820
2,048 x 2,048 channel non-blocking switching at 8.192 Mb/s
Per-channel variable or constant throughput delay
Automatic identification of ST-BUS
®
/GCI interfaces
Accept streams of 2.048 Mb/s, 4.096 Mb/s or 8.192 Mb/s
Automatic frame offset delay measurement
Per-stream frame delay offset programming
Per-channel high impedance output control
Per-channel Processor Mode
Control interface compatible to Intel/Motorola CPUs
Connection memory block programming
IEEE-1149.1 (JTAG) Test Port
Available in 84-pin Plastic Leaded Chip Carrier (PLCC),
♦
100-pin Ball Grid Array (PBGA), 100-pin Thin Plastic Quad
Flatpack (TQFP) and 100-pin Thin Quad Flatpack (TQFP)
3.3V Power Supply
DESCRIPTION:
The IDT72V70820 is a non-blocking digital switch that has a capacity of
2,048 x 2,048 channels at a serial bit rate of 8.192 Mb/s, 1,024 x 1,024 channels
at 4.096 Mb/s and 512 x 512 channels at 2.048 Mb/s. Some of the main features
are: programmable stream and channel control, Processor Mode, input offset
delay and high-impedance output control.
Per-stream input delay control is provided for managing large multi-chip
switches that transport both voice channel and concatenated data channels. In
addition, input streams can be individually calibrated for input frame offset.
FUNCTIONAL BLOCK DIAGRAM
V
CC
GND
RESET
TMS
TDI
TDO
TCK
TRST
IC
ODE
Test Port
RX0
RX1
RX2
RX3
RX4
RX5
RX6
RX7
RX8
RX9
RX10
RX11
RX12
RX13
RX14
RX15
TX0
TX1
TX2
TX3
TX4
TX5
TX6
TX7
TX8
TX9
TX10
TX11
TX12
TX13
TX14
TX15
Loopback
Receive
Serial Data
Streams
Data Memory
Output
MUX
Transmit
Serial Data
Streams
Internal
Registers
Connection
Memory
Timing Unit
Microprocessor Interface
CLK
F0i
FE/
WFPS
HCLK
AS/ IM DS/
RD
ALE
CS
R/W/ A0-A7
DTA
D8-D15/
WR
AD0-AD7
CCO
5712 drw01
MARCH 2000
1
©
2000
Integrated Device Technology, Inc.
DSC-5712/2
IDT72V70820 3.3V Time Slot Interchange
Digital Switch 2,048 x 2,048
Commercial Temperature Range
PIN CONFIGURATIONS
A
RX0
A1 BALL PAD CORNER
TX13 TX11 TX10
RX1 TX14 TX12
RX4
RX8
RX9
RX3
RX6
VCC
TX8
TX9
TX7
TX6
VCC
GND
TX4
TX5
DNC
VCC
TX3
TX2
TX1
DTA
TX0
ODE
D15
D13
D10
AD7
AD6
AD2
CCO
D14
D12
D11
D9
D8
AD5
AD3
AD0
B
RX2
C
RX5
TX15 VCC
VCC GND
GND
GND
VCC
GND
GND
D
RX7
E
RX10
GND GND VCC
GND GND
VCC
CS
VCC
AD4
AD1
F
RX11 RX12 VCC
G
RX13 RX15
CLK
GND GND
VCC
A4
A3
H
RX14
FE/
HCLK
TCK
RESET
VCC
TRST
IC
A0
WFPS
A1
A2
J
K
FOI
TMS
TDI
TDO
A7 R/W/RW IM
A5
A6
DS/RD AS/ALE
1
2
3
4
5
6
7
8
9
10
5712 drw02
PBGA (BC100-1, order code: BC)
TOP VIEW
TX15
TX14
TX13
TX12
TX11
TX10
GND
GND
GND
ODE
VCC
TX9
TX8
TX7
TX6
TX5
TX4
TX3
TX2
TX1
INDEX
RX0
RX1
RX2
RX3
RX4
RX5
RX6
RX7
RX8
RX9
RX10
RX11
RX12
RX13
RX14
RX15
F0i
FE/HCLK
GND
CLK
VCC
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75
TX0
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
CCO
DTA
D15
D14
D13
D12
D11
D10
D9
D8
GND
VCC
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
GND
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53
R/W/RW
CS
IC
RESET
WFPS
TMS
TDO
TCK
TRST
AS/ALE
TDI
A0
A1
A2
A3
A4
A5
A6
A7
DS/RD
IM
5712 drw03
NOTES:
1. DNC - Do Not Connect
2. IC - Internal Connection, tie to GROUND for normal operation.
3. All I/O pins are 5V tolerant except for TMS, TDI and
TRST.
PLCC (PL84-1, order code: J)
TOP VIEW
2
IDT72V70820 3.3V Time Slot Interchange
Digital Switch 2,048 x 2,048
Commercial Temperature Range
PIN CONFIGURATIONS (Continued)
TX13
TX12
TX15
TX14
TX11
TX10
GND
GND
GND
CCO
DNC
ODE
DNC
52
TX3
TX9
TX2
DNC
51
VCC
TX6
TX8
TX1
TX5
TX7
TX4
TX0
73
72
63
67
58
57
54
66
75
71
62
70
61
74
65
69
60
59
56
68
DNC
DNC
DNC
DNC
RX0
RX1
RX2
RX3
RX4
RX5
RX6
RX7
RX8
RX9
RX10
RX11
RX12
RX13
RX14
RX15
FOi
FE/HCLK
GND
CLK
DNC
76
77
78
79
90
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
64
55
53
DNC
DTA
D15
D14
D13
D12
D11
D10
D9
D8
GND
VCC
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
GND
DNC
DNC
DNC
DNC
16
12
21
13
17
18
22
14
23
15
10
19
2
11
WFPS
20
1
6
24
3
4
7
8
5
9
A2
A3
TDO
TCK
TRST
A0
A1
A4
A5
A6
A7
R/W/RW
CS
DS/RD
DNC
DNC
VCC
TDI
TMS
IC
INDEX
AS/ALE
DNC
RESET
IM
25
5712 drw04
TQFP (PN100-1, order code: PF)
TOP VIEW
TX13
TX12
TX15
TX11
TX14
TX10
TX9
GND
GND
GND
CCO
DNC
DNC
ODE
DNC
53
DNC
DNC
52
DNC
DNC
TX8
VCC
TX7
TX6
TX2
61
TX1
55
64
73
78
69
60
77
68
59
72
63
62
71
80
76
67
58
75
79
70
66
57
74
65
56
54
51
DNC
TX5
TX4
TX3
TX0
RX0
RX1
RX2
RX3
RX4
RX5
RX6
RX7
RX8
RX9
RX10
RX11
RX12
RX13
RX14
RX15
FOi
FE/HCLK
GND
CLK
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
DTA
D15
D14
D13
D12
D11
D10
D9
D8
GND
VCC
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
GND
23
24
10
28
11
20
25
26
29
21
22
12
13
17
14
15
18
A0
16
A4
DNC
TDI
TDO
A5
19
9
27
3
4
8
CS
AS/ALE
IM
DNC
RESET
WFPS
DNC
DNC
DNC
DNC
TRST
IC
DS/RD
INDEX
R/W/WR
DNC
VCC
DNC
A1
A6
A2
TMS
TCK
A3
A7
30
5
1
2
6
7
5712 drw05
TQFP (PK100-1, order code: TF)
TOP VIEW
3
IDT72V70820 3.3V Time Slot Interchange
Digital Switch 2,048 x 2,048
Commercial Temperature Range
PIN DESCRIPTION
SYMBOL
GND
Vcc
TX0-15
RX0-15
F0i
NAME
Ground.
Vcc
TX Output 0 to 15
(Three-state Outputs)
RX Input 0 to 15
Frame Pulse
I/O
DESCRIPTION
Ground Rail.
+3.3 Volt Power Supply.
Serial data output stream. These streams may have data rates of 2.048, 4.096 or 8.192 Mb/s, depending upon
the value programmed at bits DR0-1 in the IMS register.
Serial data input stream. These streams may have data rates of 2.048, 4.096 or 8.192 Mb/s, depending upon
the value programmed at bits DR0-1 in the IMS register.
When the WFPS pin is LOW, this input accepts and automatically identifies frame synchronization signals formatted
according to ST-BUS
®
and GCI specifications. When the WFPS pin is HIGH, this pin accepts a negative frame
pulse which conforms to WFPS formats.
When the WFPS pin is LOW, this pin is the frame measurement input. When the WFPS pin is HIGH, the HCLK
(4.096 MHz clock) is required for frame alignment in the wide frame pulse (WFP) mode.
Serial clock for shifting data in/out on the serial streams (RX/TX 0-15). Depending upon the value programmed
at bits DR0-1 in the IMS register, this input accepts a 4.096, 8.192 or 16.384 MHz clock.
JTAG signal that controls the state transitions of the TAP controller. This pin is pulled HIGH by an internal pull-
up when not driven.
JTAG serial test instructions and data are shifted in on this pin. This pin is pulled HIGH by an internal pull-up
when not driven.
JTAG serial data is output on this pin on the falling edge of TCK. This pin is held in high-impedance state when
JTAG scan is not enable.
Provides the clock to the JTAG test logic.
Asynchronously initializes the JTAG TAP controller by putting it in the Test-Logic-reset state. This pin is pulled
by an internal pull-up when not driven. This pin should be pulsed LOW on power-up, or held LOW, to ensure
that the IDT72V70820 is in the normal functional mode.
This input (active LOW) puts the IDT72V70820 in its reset state that clears the device internal counters, registers
and brings TX0-15 and microport data outputs to a high-impedance state. The time constant for a power up
reset circuit must be a minimum of five times the rise time of the power supply. In normal operation, the
RESET
pin must be held LOW for a minimum of 100ns to reset the device.
When 1, enables the wide frame pulse (WFP) Frame Alignment interface. When 0, the device operates in
ST-BUS
®
/GCI mode.
When non-multiplexed CPU bus operation is selected, these lines provide the A0-A7 address lines to the internal
memories.
For Motorola multiplexed bus operation, this input is DS. This active HIGH DS input works in conjunction with
CS
to enable the read and write operations. For Motorola non-multiplexed CPU bus operation, this input is DS. This
active LOW input works in conjunction with
CS
to enable the read and write operations. For Intel multiplexed bus
operation, this input is
RD.
This active LOW input sets the data bus lines (AD0-7, D8-15) as outputs.
In the cases of Motorola non-multiplexed and multiplexed bus operations, this input is R/W. This input controls
the direction of the data bus lines (AD0-7, D8-15) during a microprocessor access. For Intel multiplexed bus
operation, this input is
WR.
This active LOW input is used with
RD
to control the data bus (AD0-7) lines as inputs.
Active LOW input used by a microprocessor to activate the microprocessor port of IDT72V70820.
This input is used if multiplexed bus operation is selected via the IM input pin. For Motorola non-multiplexed
bus operation, connect this pin to ground.
When IM is HIGH, the microprocessor port is in the multiplexed mode. When IM is LOW, the microprocessor
port is in non-multiplexed mode.
These pins are the eight least significant data bits of the microprocessor port. In multiplexed mode, these pins
are also the input address bits of the microprocessor port.
These pins are the eight most significant data bits of the microprocessor port.
This active LOW output signal indicates that a data bus transfer is complete. When the bus cycle ends, this pin
drives HIGH and then goes high-impedance, allowing for faster bus cycles with a weaker pull-up resistor. A
pull-up resistor is required to hold a HIGH level when the pin is in high-impedance.
This is a 4.096, 8.192 or 16.384 Mb/s output containing 512, 1,024 or 2.048 bits per frame respectively. The
level of each bit is determined by the CCO bit in the connection memory. See External Drive Control Section.
This is the output enable control for the TX0 to TX15 serial outputs. When ODE input is LOW and the OSB
bit of the IMS register is LOW, TX0-15 are in a high-impedance state. If this input is HIGH, the TX0-15
output drivers are enabled. However, each channel may still be put into a high-impedance state by using the
per channel control bit in the connection memory.
4
O
I
I
FE/HCLK Frame Evaluation/
HCLK Clock
CLK
Clock
TMS
TDI
TDO
TCK
TRST
Test Mode Select
Test Serial Data In
Test Serial Data Out
Test Clock
Test Reset
I
I
I
I
O
I
I
RESET
Device Reset
(Schmitt Trigger Input)
I
WFPS
A0-7
DS/RD
Wide Frame
Pulse Select
Address 0-7
Data Strobe/Read
I
I
I
R/W /
WR
Read/Write / Write
I
CS
AS/ALE
IM
AD0-7
D8-15
DTA
Chip Select
Address Strobe or
Latch Enable
CPU Interface Mode
I
I
I
Address/Data Bus 0 to 7 I/O
Data Bus 8-15
Data Transfer
Acknowledgment
Control Output
Output Drive Enable
I/O
O
CCO
ODE
O
I
IDT72V70820 3.3V Time Slot Interchange
Digital Switch 2,048 x 2,048
Commercial Temperature Range
FUNCTIONAL DESCRIPTION
The IDT72V70820 is capable of switching up to 2,048 x 2,048, 64 Kbit/s
PCM or N x 64 Kbit/s channel data. The device maintains frame integrity in data
applications and minimum throughput delay for voice applications on a per
channel basis.
The serial input streams of the IDT72V70820 can have a bit rate of 2.048,
4.096 or 8.192 Mb/s and are arranged in 125µs wide frames, which contain
32, 64 or 128 channels respectively. The data rates on input and output streams
are identical.
In Processor Mode, the microprocessor can access input and output time-
slots on a per channel basis allowing for transfer of control and status information.
The IDT72V70820 automatically identifies the polarity of the frame synchroni-
zation input signal and configures the serial streams to either ST-BUS
®
or GCI
formats.
With the variety of different microprocessor interfaces, IDT72V70820 has
provided an Input Mode pin (IM) to help integrate the device into different
microprocessor based environments: Non-multiplexed or Multiplexed. These
interfaces provide compatibility with multiplexed and Motorola non-multiplexed
buses. The device can also resolve different control signals eliminating the use
of glue logic necessary to convert the signals (R/W/WR, DS/RD, AS/ALE).
The frame offset calibration function allows users to measure the frame offset
delay using a frame evaluation pin (FE). The input offset delay can be
programmed for individual streams using internal frame input offset registers, see
Table 11.
The internal loopback allows the TX output data to be looped around to the
RX inputs for diagnostic purposes.
A functional Block Diagram of the IDT72V70820 is shown in Figure 1.
DATA AND CONNECTION MEMORY
The received serial data is converted to parallel format by internal serial-
to-parallel converters and stored sequentially in the data memory. The 8 KHz
input frame pulse (F0i) is used to generate channel and frame boundaries of
the input serial data. Depending on the interface mode select (IMS) register,
the usable data memory may be as large as 2,048 bytes.
Data to be output on the serial streams (TX0-15) may come from either the
data memory or connection memory. For data output from data memory
(connection mode), addresses in the connection memory are used. For data
to be output from connection memory, the connection memory control bits must
set the particular TX output in Processor Mode. One time-slot before the data
is to be output, data from either connection memory or data memory is read
internally. This allows enough time for memory access and parallel-to-serial
conversion.
CONNECTION AND PROCESSOR MODES
In the Connection Mode, the addresses of the input source data for all output
channels are stored in the connection memory. The connection memory is
mapped in such a way that each location corresponds to an output channel on
the output streams. For details on the use of the source address data (CAB and
SAB bits), see Table 13 and Table 14. Once the source address bits are
programmed by the microprocessor, the contents of the data memory at the
selected address are transferred to the parallel-to-serial converters and then
onto a TX output stream.
By having the each location in the connection memory specify an input
channel, multiple outputs can specify the same input address. This can be a
powerful tool used for broadcasting data.
In Processor Mode, the microprocessor writes data to the connection
memory. Each location in the connection memory corresponds to a particular
output stream and channel number and is transferred directly to the parallel-to-
serial converter one time-slot before it is to be output. This data will be output
on the TX streams in every frame until the data is changed by the microprocessor.
As the IDT72V70820 can be used in a wide variety of applications, the device
also has memory locations to control the outputs based on operating mode.
Specifically, the IDT72V70820 provides five per-channel control bits for the
following functions: processor or connection mode, constant or variable delay,
enables/three-state the TX output drivers and enables/disable the loopback
function. In addition, one of these bits allows the user to control the CCO output.
If an output channel is set to a high-impedance state through the connection
memory, the TX output will be in a high-impedance state for the duration of that
channel. In addition to the per-channel control, all channels on the ST-BUS
®
outputs can be placed in a high impedance state by either pulling the ODE input
pin low or programming the Output Stand-By (OSB) bit in the interface mode
selection register. This action overrides the per-channel programming in the
connection memory bits.
The connection memory data can be accessed via the microprocessor
interface. The addressing of the devices internal registers, data and connection
memories is performed through the address input pins and the Memory Select
(MS) bit of the control register. For details on device addressing, see Software
Control and Control Register bits description (Table 4, 6 and 7).
SERIAL DATA INTERFACE TIMING
The master clock frequency must always be twice the data rate. For serial
data rates of 2.048, 4.096 or 8.192 Mb/s, the master clock (CLK) must be either
at 4.096, 8.192 or 16.384 MHz respectively. The input and output stream data
rates will always be identical.
The IDT72V70820 provides two different interface timing modes ST-BUS
®
/
GCI and WFP (wide frame pulse). If the WFPS pin is high, the IDT72V70820
is in the wide frame pulse (WFP) frame alignment mode.
In ST-BUS
®
/GCI mode, the input 8 KHz frame pulse can be in either
ST-BUS
®
or GCI format. The IDT72V70820 automatically detects the presence
of an input frame pulse and identifies it as either ST-BUS
®
or GCI. In ST-BUS
®
format, every second falling edge of the master clock marks a bit boundary and
the data is clocked in on the rising edge of CLK, three quarters of the way into
the bit cell, see Figure 7. In GCI format, every second rising edge of the master
clock marks the bit boundary and data is clocked in on the falling edge of CLK
at three quarters of the way into the bit cell, see Figure 8.
WIDE FRAME PULSE (WFP) FRAME ALIGNMENT TIMING
When the device is in WFP frame alignment mode, the CLK input must be
at 16.384 MHz, the FE/HCLK input is 4.096 MHz and the 8 kHz frame pulse
is in ST-BUS
®
format. The timing relationship between CLK, HCLK and the frame
pulse is shown in Figure 9.
When WFPS pin is high, the frame alignment evaluation feature is disabled.
However, the frame input offset registers may still be programmed to compensate
for the varying frame delays on the serial input streams.
5
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