NXP Semiconductors
Data Sheet: Technical Data
Document Number T4160
Rev. 1, 05/2016
QorIQ T4160/T4080 Data
Sheet
Features
• Eight e6500 cores built on Power Architecture®
technology and arranged as clusters of four e6500
cores sharing a 2 MB L2 cache (one cluster of four
e6500 cores on T4080)
• 1.0 MB CoreNet platform cache (CPC)
• Hierarchical interconnect fabric
– CoreNet fabric supporting coherent and non-
coherent transactions with prioritization and
bandwidth allocation amongst CoreNet end-points
– 1.6 Tbps coherent read bandwidth
• Two 64-bit DDR3 SDRAM memory controllers
– DDR3 and DDR3L with ECC and interleaving
support
• Data Path Acceleration Architecture (DPAA)
incorporating acceleration for the following functions:
– Packet parsing, classification, and distribution
(Frame Manager 1.1)
– Queue management for scheduling, packet
sequencing, and congestion management (Queue
Manager 1.1)
– Hardware buffer management for buffer allocation
and de-allocation (Buffer Manager 1.1)
– Cryptography Acceleration (SEC 5.0)
– RegEx Pattern Matching Acceleration (PME 2.0)
– Decompression/Compression Acceleration (DCE
1.0)
– DPAA chip-to-chip interconnect via RapidIO
Message Manager (RMan 1.0)
T4160
• 24 SerDes lanes at up to 10 GHz
• Ethernet interfaces
– Up to two 10 Gbps Ethernet MACs
– Up to 13 1 Gbps Ethernet MACs
– Combinations of 1 Gbps, 2.5 Gbps, and 10 Gbps
Ethernet MACs
– IEEE Std 1588™ support
• High-speed peripheral interfaces
– Three PCI Express 2.0/3.0 controllers running at up
to 8 Gbps with one controller supporting end-point,
single-root I/O virtualization (SR-IOV)
– Two Serial RapidIO 2.0 controllers running at up to
5 Gbaud
– Interlaken look-aside interface for TCAM
connection
• Additional peripheral interfaces
– Two Serial ATA (SATA 2.0) controllers
– Two high-speed USB 2.0 controllers with integrated
PHY
– Enhanced secure digital host controller (SD/MMC/
eMMC)
– Enhanced Serial peripheral interface (eSPI)
– Four I2C controllers
– Four 2-pin UARTs or two 4-pin DUARTs
– Integrated flash controller supporting NAND and
NOR flash
• Three 8-channel DMA engines
• 1932 FC-PBGA package, 45 mm x 45 mm, 1mm pitch
NXP reserves the right to change the production detail specifications as may be
required to permit improvements in the design of its products.
© 2014–2016 NXP B.V.
Table of Contents
1 Overview.............................................................................................. 3
2 Pin assignments.................................................................................... 4
2.1
2.2
1932 ball layout diagrams......................................................... 4
Pinout list...................................................................................10
3.16 JTAG controller.........................................................................126
3.17 I2C interface.............................................................................. 129
3.18 GPIO interface...........................................................................132
3.19 High-speed serial interfaces (HSSI).......................................... 134
4 Hardware design considerations...........................................................190
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
System clocking........................................................................ 190
Power supply design..................................................................206
Decoupling recommendations................................................... 215
SerDes block power supply decoupling recommendations.......215
Connection recommendations................................................... 216
Thermal......................................................................................227
Recommended thermal model...................................................228
Thermal management information............................................ 228
3 Electrical characteristics.......................................................................72
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
Overall DC electrical characteristics......................................... 72
Power sequencing......................................................................79
Power-down requirements.........................................................81
Power characteristics................................................................. 82
Power-on ramp rate................................................................... 93
Input clocks............................................................................... 93
RESET initialization..................................................................98
DDR3 and DDR3L SDRAM controller.................................... 99
eSPI interface.............................................................................105
5 Package information.............................................................................231
5.1
5.2
Package parameters for the FC-PBGA......................................231
Mechanical dimensions of the FC-PBGA................................. 231
3.10 DUART interface...................................................................... 108
3.11 Ethernet interface, Ethernet management interface 1 and 2,
IEEE Std 1588........................................................................... 109
3.12 USB interface............................................................................ 118
3.13 Integrated flash controller..........................................................120
3.14 Enhanced secure digital host controller (eSDHC).....................123
3.15 Multicore programmable interrupt controller (MPIC).............. 125
6 Security fuse processor.........................................................................233
7 Ordering information............................................................................233
7.1
7.2
Part numbering nomenclature....................................................233
Orderable part numbers addressed by this document................234
8 Revision history....................................................................................239
QorIQ T4160/T4080 Data Sheet, Rev. 1, 05/2016
2
NXP Semiconductors
Overview
1 Overview
The T4160 and T4080 QorIQ integrated multicore communications processor combines 8
and 4 respectively, dual-threaded cores built on Power Architecture® technology with
high-performance data path acceleration and network and peripheral bus interfaces
required for networking, telecom/datacom, wireless infrastructure, and military/aerospace
applications.
This chip can be used for combined control, data path, and application layer processing in
routers, switches, gateways, and general-purpose embedded computing systems. Its high
level of integration offers significant performance benefits compared to multiple discrete
devices, while also simplifying board design.
This figure shows the block diagram of the T4160.
Power Architecture
e6500
Power Architecture
e6500
Power Architecture
e6500
Power Architecture
e6500
32 KB
D-Cache
32 KB
I-Cache
32 KB
D-Cache
32 KB
I-Cache
32 KB
D-Cache
32 KB
I-Cache
32 KB
D-Cache
32 KB
I-Cache
512 KB
Plat Cache
512 KB
Plat Cache
64-bit DDR3/3L
with ECC
64-bit DDR3/3L
with ECC
2 MB banked L2
MPIC
PreBoot Loader
Security monitor
Internal BootROM
Power mgmt
SD/MMC
eSPI
4 x UART
4x I
2
C
IFC
2 x USB 2.0 w/ PHY
Clocks/Reset
GPIO
CCSR
DCE
RMan
1/10G
CoreNet
TM
Coherency Fabric
PAMU
PAMU
PAMU (peripheral access management unit)
PME
BMan
Buffer
1G 1G 1G
1G 1G
1/10G
Buffer
1G
1G 1G 1G
SATA 2.0
SATA 2.0
Parse, classify,
distribute
Parse, classify,
distribute
InterlakenLA-1
SEC
QMan
FMan
FMan
DMAx3
Real-time
debug
Watch point
cross-
trigger
Perf
Monitor
Trace
sRIO
sRIO
PCIe
PCIe
PCIe
1G 1G 1G
Aurora
12 lanes up to 10 GHz SerDes
12 lanes up to 10 GHz SerDes
Figure 1. T4160 Block diagram
This figure shows the block diagram of the T4080.
QorIQ T4160/T4080 Data Sheet, Rev. 1, 05/2016
NXP Semiconductors
3
Pin assignments
Power Architecture
e6500
Power Architecture
e6500
Power Architecture
e6500
Power Architecture
e6500
32 KB
D-Cache
32 KB
I-Cache
32 KB
D-Cache
32 KB
I-Cache
32 KB
D-Cache
32 KB
I-Cache
32 KB
D-Cache
32 KB
I-Cache
512 KB
Plat Cache
512 KB
Plat Cache
64-bit DDR3/3L
with ECC
64-bit DDR3/3L
with ECC
2 MB banked L2
MPIC
PreBoot Loader
Security monitor
Internal BootROM
Power mgmt
SD/MMC
eSPI
4 x UART
4x I
2
C
IFC
2 x USB 2.0 w/ PHY
Clocks/Reset
GPIO
CCSR
DCE
RMan
1/10G
CoreNet
TM
Coherency Fabric
PAMU
PAMU
PAMU (peripheral access management unit)
SATA 2.0
PME
BMan
Buffer
1G 1G 1G
1G 1G
1/10G
Buffer
1G
1G 1G 1G
SATA 2.0
Parse, classify,
distribute
Parse, classify,
distribute
InterlakenLA-1
SEC
QMan
FMan
FMan
3x DMA
Real-time
debug
Watch point
cross-
trigger
Perf
Monitor
Trace
sRIO
sRIO
PCIe
PCIe
PCIe
1G 1G 1G
Aurora
12 lanes up to 10 GHz SerDes
12 lanes up to 10 GHz SerDes
Figure 2. T4080 Block diagram
2 Pin assignments
2.1 1932 ball layout diagrams
This figure shows the complete view of the T4160 and T4080 ball map diagram.
Figure
4, Figure 5, Figure 6,
and
Figure 7
show quadrant views.
QorIQ T4160/T4080 Data Sheet, Rev. 1, 05/2016
4
NXP Semiconductors
Pin assignments
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
AG
AH
AJ
AK
AL
AM
AN
AP
AR
AT
AU
AV
AW
AY
BA
BB
BC
BD
A
B
C
D
E
F
G
H
SEE DETAIL A
SEE DETAIL B
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
AG
AH
AJ
AK
SEE DETAIL C
SEE DETAIL D
AL
AM
AN
AP
AR
AT
AU
AV
AW
AY
BA
BB
BC
BD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
DDR Interface 1
DDR Interface 2
IFC
DUART
I2C
eSPI
eSDHC
MPIC
LP Trust
Trust
System Control
ASLEEP
Clocking
DDR Clocking
Debug
DFT
JTAG
SerDes 1
SerDes 2
SerDes 3
SerDes 4
USB PHY 1 and 2
USB CLK
IEEE1588
Ethernet MI 1
Ethernet MI 2
Ethernet Cont. 1
Ethernet Cont. 2
DMA
Analog signals
Power
Ground
No Connects
Reserved
Figure 3. Complete BGA Map for the T4160
QorIQ T4160/T4080 Data Sheet, Rev. 1, 05/2016
NXP Semiconductors
5
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