PLDC20G10B/PLDC20G10
CMOS Generic 24-Pin
Reprogrammable Logic Device
Features
• Fast
— Commercial: t
PD
= 15 ns, t
CO
= 10 ns, t
S
= 12 ns
— Military: t
PD
= 20 ns, t
CO
= 15 ns, t
S
= 15 ns
• Low power
— I
CC
max.: 70 mA, commercial
— I
CC
max.: 100 mA, military
• Commercial and military temperature range
• User-programmable output cells
— Selectable for registered or combinatorial operation
— Output polarity control
— Output enable source selectable from pin 13 or prod-
uct term
• Generic architecture to replace standard logic func-
tions including: 20L10, 20L8, 20R8, 20R6, 20R4, 12L10,
14L8, 16L6, 18L4, 20L2, and 20V8
• Eight product terms and one OE product term per out-
put
• CMOS EPROM technology for reprogrammability
• Highly reliable
— Uses proven EPROM technology
— Fully AC and DC tested
— Security feature prevents logic pattern duplication
—
±10%
power supply voltage and higher noise immu-
nity
Functional Description
Cypress PLD devices are high-speed electrically programma-
ble logic devices. These devices utilize the sum-of-products
(AND-OR) structure providing users the ability to program cus-
tom logic functions for unique requirements.
In an unprogrammed state the AND gates are connected via
EPROM cells to both the true and complement of every input.
By selectively programming the EPROM cells, AND gates may
be connected to either the true or complement or disconnected
from both true and complement inputs.
Logic Block Diagram
V
SS
12
I
11
I
10
I
9
I
8
I
7
I
6
I
5
I
4
I
3
I
2
CP/I
1
PROGRAMMABLE
ANDARRAY
8
8
8
8
8
8
8
8
8
8
OE
OUTPUT
CELL
OUTPUT
CELL
OE
OUTPUT
CELL
OE
OUTPUT
CELL
OE
OUTPUT
CELL
OE
OE
OE
OE
OUTPUT
CELL
OUTPUT
CELL
OUTPUT
CELL
OUTPUT
CELL
OUTPUT
CELL
13
I/OE
14
I/O
9
15
I/O
8
16
I/O
7
17
I/O
6
18
I/O
5
19
I/O
4
20
I/O
3
21
I/O
2
22
I/O
1
23
I/O
0
24
V
CC
20G10–1
Pin Configurations
LCC
Top View
NC
I
I
CP/I
V
CC
I/O 0
I/O 1
STD PLCC
Top View
I
I
I
CP/I
V CC
I/O0
I/O1
JEDEC PLCC
Top View
I
I
CP/I
NC
V CC
I/O0
I/O 1
4 3 2 1 2827 26
I/O
2
I/O
3
I/O
4
I/O
5
I/O
6
I/O
7
NC
I
I
I
NC
I
I
I
5
6
7
8
9
10
11
[1]
I
I
I
I
I
I
NC
5
6
7
8
9
10
11
4 3 2 1 282726
25
24
23
PLDC20G10 22
PLDC20G10B
21
20
19
12131415161718
V SS
I/OE
I/O9
I/O8
NC
4 3 2 1 2827 26
NC
I/O
2
I/O
3
I/O
4
I/O
5
I/O
6
I/O
7
NC
I
I
NC
I
I
NC
5
6
7
8
9
10
11
25
24
23
PLDC20G10
PLDC20G10B 22
21
20
121314 1516 1718 19
V
SS
I/OE
I/O 9
I/O 8
25
24
23
CG7C323–A
CG7C323B–A 22
21
20
121314 1516 1718 19
VSS
NC
I/OE
I/O 9
I/O 8
I/O
2
I/O
3
I/O
4
NC
I/O
5
I/O
6
I/O
7
Note:
1. The CG7C323 is the PLDC20G10 packaged in the JEDEC-compatible 28-pin PLCC pinout. Pin function and pin order is identical for both PLCC pinouts.
The difference is in the location of the “no connect” or NC pins.
Cypress Semiconductor Corporation
Document #: 38-03010 Rev. **
I
I
I
I
I
I
I
20G10–2
20G10–4
20G10–3
•
3901 North First Street
•
San Jose
•
CA 95134 • 408-943-2600
Revised March 26, 1997
PLDC20G10B/PLDC20G10
Selection Guide
I
CC
(mA)
Generic
Part Number
20G10B–15
20G10B–20
20G10B–25
20G10–25
20G10–30
20G10–35
20G10–40
55
80
55
80
35
40
Com/Ind
70
70
100
100
25
30
30
35
Mil
t
PD
(ns)
Com/Ind
15
20
20
25
15
20
25
25
Mil
t
S
(ns)
Com/Ind
12
12
15
18
15
20
Mil
t
CO
(ns)
Com/Ind
10
12
15
15
Mil
Functional Description
(continued)
Cypress PLDC20G10 uses an advanced 0.8-micron CMOS
technology and a proven EPROM cell as the programmable
element. This technology and the inherent advantage of being
able to program and erase each cell enhances the reliability
and testability of the circuit. This reduces the burden on the
customer to test and to handle rejects.
A preload function allows the registered outputs to be preset
to any pattern during testing. Preload is important for testing
the functionality of the Cypress PLD device.
Table and in
Figures 1
through
8.
A total of eight different con-
figurations are possible, with the two most common shown in
Figure 3
and
Figure 5.
The default or unprogrammed state is
registered/active/LOW/Pin 11 OE. The entire programmable
output cell is shown in the next section.
The architecture bit ‘C1’ controls the registered/combinatorial
option. In either combinatorial or registered configuration, the
output can serve as an I/O pin, or if the output is disabled, as
an input only. Any unused inputs should be tied to ground. In
either registered or combinatorial configuration, the output of
the register is fed back to the array. This allows the creation of
control-state machines by providing the next state. The regis-
ter is clocked by the signal from Pin 1. The register is initialized
on power up to Q output LOW and Q output HIGH.
In both the combinatorial and registered configurations, the
source of the output enable signal can be individually chosen
with architecture bit ‘C2’. The OE signal may be generated
within the array, or from the external OE (Pin 13). The Pin 13
allows direct control of the outputs, hence having faster en-
able/disable times.
Each output cell can be configured for output polarity. The out-
put can be either active HIGH or active LOW. This option is
controlled by architecture bit ‘C0’.
Along with this increase in functional density, the Cypress
PLDC20G10 provides lower-power operation through the use
of CMOS technology and increased testability with a register
preload feature.
20G10 Functional Description
The PLDC20G10 is a generic 24-pin device that can be pro-
grammed to logic functions that include but are not limited to:
20L10, 20L8, 20R8, 20R6, 20R4, 12L10, 14L8, 16L6, 18L4,
20L2, and 20V8. Thus, the PLDC20G10 provides significant
design, inventory and programming flexibility over dedicated
24-pin devices. It is executed in a 24-pin 300-mil molded DIP
and a 300-mil windowed cerDIP. It provides up to 22 inputs and
10 outputs. When the windowed cerDIP is exposed to UV light,
the 20G10 is erased and then can be reprogrammed.
The programmable output cell provides the capability of defin-
ing the architecture of each output individually. Each of the 10
output cells may be configured with registered or combinatorial
outputs, active HIGH or active LOW outputs, and product term
or Pin 13 generated output enables. Three architecture bits
determine the configurations as shown in the Configuration
Document #: 38-03010 Rev. **
Page 2 of 13
PLDC20G10B/PLDC20G10
Programmable Output Cell
OE PRODUCT TERM
OUTPUT
ENABLE
MUX
C
2
10
11
OUTPUT
SELECT
MUX
00
D
Q
01
CP
0
INPUT/
FEED–
BACK
MUX
C
3
C
2
C
1
C
0
Q
C
1
C
0
1
PIN 13
20G10–5
Configuration Table
Figure
1
2
5
6
3
4
7
8
C
2
0
0
0
0
1
1
1
1
C
1
0
0
1
1
0
0
1
1
C
0
0
1
0
1
0
1
0
1
Configuration
Product Term OE/Registered/Active LOW
Product Term OE/Registered/Active HIGH
Product Term OE/Combinatorial/Active LOW
Product Term OE/Combinatorial/Active HIGH
Pin 13 OE/Registered/Active LOW
Pin 13 OE/Registered/Active HIGH
Pin 13 OE/Combinatorial/Active LOW
Pin 13 OE/Combinatorial/Active HIGH
Document #: 38-03010 Rev. **
Page 3 of 13
PLDC20G10B/PLDC20G10
Registered Output Configurations
C
2
= 0
C
1
= 0
C
0
= 0
CP
D
Q
D
Q
C
2
= 0
C
1
= 0
C
0
= 1
CP
Q
Q
20G10–6
20G10–7
Figure 1. Product Term OE/Active LOW
Figure 2. Product Term OE/Active HIGH
D
Q
C
2
= 1
C
1
= 0
C
0
= 0
CP
D
Q
C
2
= 1
C
1
= 0
C
0
= 1
CP
Q
Q
20G10–8
20G10–9
Figure 3. Pin 13 OE/Active LOW
Figure 4. Pin 13 OE/Active HIGH
Combinatorial Output Configurations
[2]
C
2
= 0
C
1
= 1
C
0
= 0
C
2
= 0
C
1
= 1
C
0
= 1
20G10–10
20G10–11
Figure 5. Product Term OE/Active LOW
Figure 6. Product Term OE/Active HIGH
C
2
= 1
C
1
= 1
C
0
= 0
C
2
= 1
C
1
= 1
C
0
= 1
20G10–12
PIN 13
PIN 13
20G10–13
Figure 7. Pin 13 OE/Active Low
Figure 8. Pin 13 OE/Active HIGH
Note:
2. Bidirectional I/O configurations are possible only when the combinatorial output option is selected
Document #: 38-03010 Rev. **
Page 4 of 13
PLDC20G10B/PLDC20G10
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Supply Voltage to Ground Potential ............... –0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State ............................................... –0.5V to +7.0V
DC Input Voltage............................................ –3.0V to +7.0V
Output Current into Outputs (LOW) .............................16 mA
DC Programming Voltage
PLDC20G10B and CG7C323B–A ............................... 13.0V
PLDC20G10 and CG7C323–A.................................... 14.0V
Latch-Up Current..................................................... >200 mA
Static Discharge Voltage ............................................. >500V
(per MIL-STD-883, Method 8015)
Operating Range
Range
Commercial
Military
[3]
Industrial
]
Ambient
Temperature
0
°
C to +75
°
C
–55
°
C to +125
°
C
–40
°
C to +85
°
C
V
CC
5V
±10%
5V
±10%
5V
±10%
Electrical Characteristics
Over the Operating Range (Unless Otherwise Noted)
[4]
Parameter
V
OH
V
OL
V
IH
V
IL
I
IX
I
SC
I
CC
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Level
Input LOW Level
Input Leakage Current
Power Supply Current
V
CC
= Min.,
V
IN
= V
IH
or V
IL
V
CC
= Min.,
V
IN
= V
IH
or V
IL
Test Conditions
I
OH
= –3.2 mA
I
OH
= –2 mA
I
OL
= 24 mA
I
OL
= 12 mA
Com’l/Ind
Military
Com’l/Ind
Military
2.0
0.8
–10
Com’l/Ind–15, –20
Com’l/Ind–25, –35
Military–20, –25
Military–30, –40
I
OZ
Output Leakage Current
V
CC
= Max., V
SS
≤
V
OUT
≤
V
CC
–100
+10
–90
70
55
100
80
100
V
V
µA
mA
mA
mA
mA
mA
µA
0.5
V
Min.
2.4
Max.
Unit
V
Guaranteed Input Logical HIGH Voltage for All Inputs
[5]
Guaranteed Input Logical LOW Voltage for All Inputs
[5]
V
SS
≤
V
IN
≤
V
CC
0
≤
V
IN
≤
V
CC
V
CC
= Max.,
I
OUT
= 0 mA
Unprogrammed Device
Output Short Circuit Current V
CC
= Max., V
OUT
= 0.5V
[6, 7]
Capacitance
[7]
Parameter
C
IN
C
OUT
Description
Input Capacitance
Output Capacitance
Test Conditions
T
A
= 25
°
C, f = 1 MHz
V
IN
= 2.0V, V
CC
= 5.0V
Max.
10
10
Unit
pF
pF
Notes:
3. T
A
is the “instant on” case temperature.
4. See the last page of this specification for Group A subgroup testing information.
5. These are absolute values with respect to device ground. All overshoots due to system or tester noise are included.
6. Not more than one output should be tested at a time. Duration of the short circuit should not be more than one second. V
OUT
= 0.5V has been chosen to avoid
test problems caused by tester ground degradation.
7. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-03010 Rev. **
Page 5 of 13
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