DS2404
EconoRAM Time Chip
www.maxim-ic.com
FEATURES
§
4096 bits of nonvolatile dual-port memory
including real time clock/calendar in binary
format, programmable interval timer, and
programmable power-on cycle counter
1-Wire
®
interface for MicroLAN
communication at 16.3kbits/s
3-wire host interface for high-speed data
communications at 2Mb/s
Unique, factory-lasered and tested 64-bit
registration number (8-bit family code +
48-bit serial number + 8-bit CRC tester)
assures absolute traceability because no two
parts are alike
Memory partitioned into 16 pages of 256-bits
for packetizing data
256-bit scratchpad with strict read/write
protocols ensures integrity of data transfer
Programmable alarms can be set to generate
interrupts for interval timer, real time clock,
and/or cycle counter
16-pin DIP, SO, and SSOP packages
Operating temperature range from -40°C to
+85°C
Operating voltage range from 2.8V to 5.5V
16-pin DIP
16-pin SO
16-pin SSOP
Tape and Reel of S2404S-001
Tape and Reel of DS2404B
PIN ASSIGNMENT
VCC
IRQ
1
2
16
15
VCC
X1
RST
DQ
I/O
CLK
NC
GND
3
4
5
6
7
8
14
13
12
11
10
9
X2
GND
NC
1HZ
VBATO
VBATB
§
§
§
§
§
§
§
§
§
16-PIN DIP (300 MIL)
16-PIN SO (300 MIL)
16-PIN SSOP (208 MIL)
See Mechanical Drawings Section
PIN DESCRIPTION
V
CC
IRQ
RST
DQ
I/O
CLK
NC
GND
V
BATB
V
BATO
1Hz
X
1
, X2
–
–
–
–
–
–
–
–
–
–
–
–
2.8 to 5.5V
Interrupt Output
3-Wire Reset Input
3-Wire Input/Output
1-Wire Input/Output
3-Wire Clock Input
No Connection
Ground
Battery Backup Input
Battery Operate Input
1Hz Output
Crystal Connections
ORDERING INFORMATION
DS2404-001
DS2404S-001
DS2404B
DS2404S-001/T&R
DS2404B/T&R
DESCRIPTION
The DS2404 EconoRAM Time Chip offers a simple solution for storing and retrieving vital data and time
information with minimal hardware. The DS2404 contains a unique lasered ROM, real-time
clock/calendar, interval timer, cycle counter, programmable interrupts, and 4096-bits of SRAM. Two
separate ports are provided for communication: 1-Wire and 3-wire. Using the 1-Wire port, only one pin is
required for communication, and the lasered-ROM can be read even when the DS2404 is without power.
The 3-wire port provides high-speed communication using the traditional Dallas Semiconductor 3-wire
interface. With either interface, a strict protocol for accessing the DS2404 ensures data integrity. Utilizing
backup energy sources, the data is nonvolatile (NV) and allows for stand-alone operation.
1 of 29
110501
DS2404
The DS2404 features can be used to create a stopwatch, alarm clock, time and date stamp, logbook, hour
meter, calendar, system power-cycle timer, expiration timer, and event scheduler.
DETAILED PIN DESCRIPTION
PIN
1,16
2
3
4
5
6
7,12
8,13
9
10
11
14,15
SYMBOL
V
CC
DESCRIPTION
Power input pins
for V
CC
operate mode. 2.8V to 5.5V operation. Either
one can be used for V
CC.
Only one is required for normal operation. (See
V
BATO
pin description and “Power Control” section).
Interrupt output pin.
Open drain.
Reset input pin
for 3-wire operation. (See “Parasite Power” section.)
Data input/output pin
for 3-wire operation.
Data input/output
for 1-Wire operation: Open drain. (See “Parasite
Power” section.)
Clock input pin
for 3-wire operation.
No connection pins.
Ground pin.
Either pin can be used for ground.
Battery backup input pin.
Battery voltage can be 2.8V to 5.5V. (See
V
BATO
pin description and “Power Control” section.)
Battery operate input pin
for 2.8V to 5.5V operation. The V
CC
&
V
BATB
pins must be grounded when this pin is used to power the chip.
(See “Power Control” section.)
1Hz square wave output:
Open drain.
Crystal pins.
Connections for a standard 32.768kHz quartz crystal,
EPSON part number C-002RX or C-004R (be sure to request 6pF load
capacitance).
NOTE:
X1 and X2 are very high impedance nodes. It is recommended
that they and the crystal be guard-ringed with ground and that high
frequency signals be kept away from the crystal area. See Figure 18 and
Application Note 58 for details.
IRQ
RST
DQ
I/O
CLK
NC
GND
V
BATB
V
BATO
1Hz
X
1
,X
2
OVERVIEW
The DS2404 has four main data components: 1) 64-bit lasered ROM, 2) 256-bit scratchpad, 3) 4096-bit
SRAM, and 4) timekeeping registers. The timekeeping section utilizes an on-chip oscillator that is
connected to an external 32.768kHz crystal. The SRAM and timekeeping registers reside in one
contiguous address space referred to hereafter as memory. All data is read and written least significant bit
first.
Two communication ports are provided a 1-Wire port and a 3-wire port. A port selector determines which
of the two ports is being used. The communication ports and the ROM are parasite-powered via I/O,
RST
, or V
CC
. This allows the ROM to be read in the absence of power. The ROM data is accessible only
through the 1-Wire port. The scratchpad and memory are accessible via either port.
If the 3-wire port is used, the master provides one of four memory function commands: 1) read memory,
2) read scratchpad, 3) write scratchpad, or 4) copy scratchpad. The only way to write memory is to first
write the scratchpad and then copy the scratchpad data to memory. (See Figure 6.)
If the 1-Wire port is used, the memory functions will not be available until the ROM function protocol
has been established. This protocol is described in the ROM functions flow chart (Figure 9). The master
must first provide one of five ROM function commands: 1) read ROM, 2) match ROM, 3) search ROM,
2 of 29
DS2404
4) skip ROM or 5) search interrupt. After a ROM function sequence has been successfully executed, the
memory functions are accessible and the master may then provide any one of the four memory function
commands (Figure 6).
The “Power Control” section provides for two basic power configurations: battery operate mode and V
CC
operate mode. The battery operate mode utilizes one supply connected to V
BATO
. The V
CC
operate mode
may utilize two supplies; the primary supply connects to V
CC
and a backup supply connects to V
BATB
.
DS2404 BLOCK DIAGRAM
Figure 1
COMMUNICATION PORTS
Two communication ports are provided: a 1-Wire and a 3-wire port. The advantages of using the 1-Wire
port are as follows: 1) provides access to the 64-bit lasered ROM, 2) consist of a single communication
signal (I/O), and 3) multiple devices may be connected to the 1-Wire bus. The 1-Wire bus has a
maximum data rate of 16.3kbits/s and requires one 5kW external pull-up.
The 3-wire port consists of three signals:
RST
, CLK, and DQ.
RST
is an enable input, DQ is bidirectional
serial data, and the CLK input is used to clock in or out the serial data. The advantages of using the
3-wire port are 1) high data transfer rate (2MHz), 2) simple timing, and 3) no external pull-up required.
3 of 29
DS2404
Port selection is accomplished on a first-come, first-serve basis. Whichever port comes out of reset first
will obtain control. For the 3-wire port, this is done by bringing
RST
high. For the 1-Wire port, this is
done on the first falling edge of I/O after the reset and presence pulses. (See “1-Wire Signaling” section.)
More information on how to arbitrate port access is found in section “Device Operation Modes” later in
this document.
PARASITE POWER
The block diagram (Figure 1) shows the parasite-powered circuitry. This circuitry “steals” power
whenever the I/O,
RST
, or V
CC
pins are high. When using the 1-Wire port in battery operate mode,
RST
and V
CC
provide no power since they are low. However, I/O will provide sufficient power as long as
the specified timing and voltage requirements are met. The advantages of parasite power are two-fold:
1) by parasiting off these pins, battery power is conserved and 2) the ROM may be read in absence of
normal power. For instance, in battery-operate mode, if the battery fails, the ROM may still be read
normally.
In battery-backed mode, if V
CC
fails, the port switches in the battery but inhibits communication. The
ROM may still be read normally over the 1-Wire port if
RST
is low.
64-BIT LASERED ROM
Each DS2404 contains a unique ROM code that is 64 bits long. The first eight bits are a 1-Wire family
code (DS2404 code is 04h). The next 48 bits are a unique serial number. The last eight bits are a CRC of
the first 56 bits. (See Figure 2.)
The 1-Wire CRC is generated using a polynomial generator consisting of a shift register and XOR gates
as shown in Figure 3. The polynomial is X
8
+ X
5
+ X
4
+ 1. Additional information about the Dallas
1-Wire Cyclic Redundancy Check is available in Application Note 27, “Understanding and Using Cyclic
Redundancy Checks with Dallas Semiconductor iButton Products”.
The shift register bits are initialized to zero. Then starting with the least significant bit of the family code,
one bit at a time is shifted in. After the 8th bit of the family code has been entered, then the serial number
is entered. After the 48th bit of the serial number has been entered, the shift register contains the CRC
value. Shifting in the eight bits of CRC should return the shift register to all zeros.
64-BIT LASERED ROM
Figure 2
CRC
8 BITS
MSB
SERIAL NUMBER
48-BIT UNQUE NUMBER
DS2404 FAMILY CODE
04h
LSB
1-WIRE CRC CODE
Figure 3
4 of 29
DS2404
MEMORY MAP
Figure 4
5 of 29
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
