High Performance 2A and 3A Linear Regulators
ISL80102, ISL80103
The ISL80102 and ISL80103 are low voltage,
high-current, single output LDOs specified for 2A and 3A
output current, respectively. These LDOs operate from
input voltages of 2.2V to 6V and are capable of providing
output voltages of 0.8V to 5V on the adjustable V
OUT
versions. Fixed output voltage options are available in
1.5V, 1.8V, 2.5V, 3.3V and 5V. Other custom voltage
options available upon request.
For applications that demand in-rush current less than
the current limit, an external capacitor on the soft start
pin provides adjustment. The ENABLE feature allows the
part to be placed into a low quiescent current shutdown
mode. A sub-micron BiCMOS process is utilized for this
product family to deliver the best in class analog
performance and overall value.
These CMOS LDOs will consume significantly lower
quiescent current as a function of load over bipolar LDOs,
which translates into higher efficiency and the ability to
consider packages with smaller footprints. Quiescent
current is modestly compromised to enable a leading
class fast load transient response, and hence a lower
total AC regulation band for an LDO in this category.
ISL80102, ISL80103
Features
• Stable with all Capacitor Types (Note 11)
• 2A and 3A Output Current Ratings
• 2.2V to 6V Input Voltage Range
• ±1.8% V
OUT
Accuracy Guaranteed Over Line, Load
and T
J
= -40°C to +125°C
• Very Low 120mV Dropout Voltage at 3A (ISL80103)
• Fixed and Adjustable V
OUT
Versions
• Very Fast Transient Response
• Excellent 62dB PSRR
• 100µV
RMS
Output Noise
• Power-Good Output
• Adjustable In-Rush Current Limiting
• Short Circuit and Over-Temperature Protection
• Available in a 10 Ld DFN (now), 5Ld TO220 and 5Ld
TO263 (soon)
Applications*
(see page 14)
• Servers
• Telecommunications and Networking
• Medical Equipment
• Instrumentation Systems
• Routers and Switchers
Typical Application
ISL80102, ISL80103
2.5V ±10%
V
IN
C
IN
10µF
1.8V ±1.8%
9
10
VIN
VIN
VOUT
VOUT
1
2
C
OUT
10µF
V
OUT
R
PG
ON
OFF
7
6
*C
SS
ENABLE
SS
GND
5
*CSS is optional, (see Note 12) on page 5.
SENSE
3
100kΩ
4
PG
PGOOD
March 22, 2010
FN6660.1
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2009, 2010. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL80102, ISL80103
Block Diagram
VIN
R5
10µA
10µA
M5
M4
M3
M1
POWER PMOS
IL
LEVEL
SHIFT
-
+
EN
500mV
R4
IL/10,000
VOUT
R8
R7
R9
+
-
EN
EN
+
-
M6
R1
R2
SENSE
ADJ
PG
M2
*R3
GND
EN
ENABLE
SS
M8
EN
M7
V TO I
500mV +
-
485mV
+
-
-
+
*R3 is open for ADJ versions.
Ordering Information
PART NUMBER
(Notes 1, 2, 4)
ISL80102IRAJZ
ISL80102IR15Z
ISL80102IR18Z
ISL80102IR25Z
ISL80102IR33Z
ISL80102IR50Z
ISL80103IRAJZ
ISL80103IR15Z
ISL80103IR18Z
ISL80103IR25Z
ISL80103IR33Z
ISL80103IR50Z
NOTES:
1. Add “-T” or “-TK” suffix for tape and reel. Please refer to
TB347
for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach
materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both
SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. The 1.5V, 3.3V and 5V fixed output voltages will be released in the future. Please contact Intersil Marketing for more details.
4. For Moisture Sensitivity Level (MSL), please see device information page for
ISL80102, ISL80103.
For more information on
MSL please see tech brief
TB363.
PART
MARKING
DZJA
DZMA
DZNA
DZPA
DZRA
DZSA
DZAA
DZDA
DZEA
DZFA
DZGA
DZHA
V
OUT
VOLTAGE
ADJ
1.5V (Note 3)
1.8V
2.5V
3.3V (Note 3)
5.0V (Note 3)
ADJ
1.5V (Note 3)
1.8V
2.5V
3.3V (Note 3)
5.0V (Note 3)
TEMP. RANGE
(°C)
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
PACKAGE
(Pb-Free)
10 Ld 3x3 DFN
10 Ld 3x3 DFN
10 Ld 3x3 DFN
10 Ld 3x3 DFN
10 Ld 3x3 DFN
10 Ld 3x3 DFN
10 Ld 3x3 DFN
10 Ld 3x3 DFN
10 Ld 3x3 DFN
10 Ld 3x3 DFN
10 Ld 3x3 DFN
10 Ld 3x3 DFN
PKG
DWG. #
L10.3x3
L10.3x3
L10.3x3
L10.3x3
L10.3x3
L10.3x3
L10.3x3
L10.3x3
L10.3x3
L10.3x3
L10.3x3
L10.3x3
2
FN6660.1
March 22, 2010
ISL80102, ISL80103
Pin Configuration
ISL80102, ISL80103
(10 LD 3X3 DFN)
TOP VIEW
V
OUT
V
OUT
SENSE/ADJ
PG
GND
1
2
3
4
5
10 V
IN
9 V
IN
8 DNC
7 ENABLE
6 SS
Pin Descriptions
PIN NUMBER
1, 2
3
4
5
6
7
8
9, 10
PIN NAME
V
OUT
SENSE/ADJ
PG
GND
SS
ENABLE
DNC
V
IN
EPAD
Output voltage pin.
Remote voltage sense for internally fixed V
OUT
options. ADJ pin for externally set V
OUT
.
V
OUT
in regulation signal. Logic low defines when V
OUT
is not in regulation. Must be grounded if
not used.
GND pin.
External cap adjusts in-rush current.
V
IN
independent chip enable. TTL and CMOS compatible.
Do not connect this pin to ground or supply. Leave floating.
Input supply pin.
EPAD at ground potential. Soldering it directly to GND plane is optional.
DESCRIPTION
Typical Application
ISL80102, ISL80103
2.5V ±10%
V
IN
C
IN
10µF
R
1
10kΩ
7
6
PG
ENABLE
**C
PB
SS
GND
5
*CSS is optional, (see Note 12) on page 5.
**C
PB
is optional. See “Functional Description” on page 12 for more information.
ADJ
3
1500pF
R
3
2.61kΩ
4
PGOOD
1.8V
9
10
VIN
VIN
VOUT
VOUT
1
2
C
OUT
10µF
R
PG
100kΩ
V
OUT
EN
OPEN DRAIN COMPATIBLE
*C
SS
R
4
1.0kΩ
FIGURE 1. TYPICAL APPLICATION DIAGRAM
3
FN6660.1
March 22, 2010
ISL80102, ISL80103
Absolute Maximum Ratings
(Note 7)
V
IN
relative to GND . . . . . . . . . . . . . . . . . . -0.3V to +6.5V
V
OUT
relative to GND . . . . . . . . . . . . . . . . . -0.3V to +6.5V
PG, ENABLE, SENSE/ADJ, SS
Relative to GND. . . . . . . . . . . . . . . . . . . . -0.3V to +6.5V
Thermal Information
Thermal Resistance (Typical)
θ
JA
(°C/W)
θ
JC
(°C/W)
10 Ld 3x3 DFN Package (Notes 5, 6)
48
4
Maximum Junction Temperature (Plastic Package). . . +150°C
Storage Temperature Range . . . . . . . . . . . -65°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
(Note 10)
Junction Temperature Range (T
J
) . .
VIN relative to GND . . . . . . . . . . . .
V
OUT
range . . . . . . . . . . . . . . . . . .
PG, ENABLE, SENSE/ADJ, SS relative
PG sink current . . . . . . . . . . . . . . .
. . . . . -40°C to +125°C
. . . . . . . . . 2.2V to 6V
. . . . . . . . 800mV to 5V
to GND . . . . . 0V to 6V
. . . . . . . . . . . . . 10mA
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact
product reliability and result in failures not covered by warranty.
NOTES:
5.
θ
JA
is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach”
features. See Tech Brief TB379.
6. For
θ
JC
, the “case temp” location is the center of the exposed metal pad on the package underside.
7. ABS max voltage rating is defined as the voltage applied for a lifetime average duty cycle above 6V of 1%.
Electrical Specifications
Unless otherwise noted, all parameters are established over the following specified
conditions: V
IN
= V
OUT
+ 0.4V, V
OUT
= 1.8V, C
IN
= C
OUT
= 10µF, T
J
= +25°C, I
LOAD
= 0A
Applications must follow thermal guidelines of the package to determine worst case junction
temperature. Please refer to “Functional Description” on page 12 and Tech Brief
TB379.
Boldface limits apply over the operating temperature range, -40°C to +125°C.
Pulse load techniques used by ATE to ensure T
J
= T
A
defines established limits.
SYMBOL
TEST CONDITIONS
MIN
MAX
(Note 8) TYP (Note 8) UNITS
PARAMETER
DC CHARACTERISTICS
DC Output Voltage Accuracy
V
OUT
V
OUT
Options: 1.8V.
V
IN
=2.2V; I
LOAD
= 0A
V
OUT
Options: 1.8V.
2.2V < V
IN
< 3.6V; 0A < I
LOAD
< 3A
V
OUT
Options: 2.5V
V
IN
=V
OUT
+ 0.4V; I
LOAD
= 0A
V
OUT
Options: 2.5V
V
OUT
+ 0.4V < V
IN
< 6V; 0A < I
LOAD
< 3A
-1.8
491
-1.8
0.5
1.8
0.5
-1.8
500
0.1
0.1
-0.8
-0.6
0.01
7.5
8.5
0.4
3.3
120
81
16
185
125
1
9
12
509
0.4
0.8
%
%
%
%
mV
%
%
%
%
µA
mA
mA
µA
µA
mV
mV
Feedback Pin (ADJ Version)
DC Input Line Regulation
V
FB
ΔV
OUT
/ΔV
IN
2.2V < V
IN
< 6V, 0A < I
LOAD
< 3A
V
OUT
+ 0.4V < V
IN
< 3.6V, V
OUT
= 1.8V
V
OUT
+ 0.4V < V
IN
< 6V, V
OUT
= 2.5V
DC Output Load Regulation
ΔV
OUT
/ΔI
OUT
0A < I
LOAD
< 3A, All voltage options
0A < I
LOAD
< 2A, All voltage options
V
ADJ
= 0.5V
I
Q
I
SHDN
V
DO
I
LOAD
= 0A, 2.2V < V
IN
< 6V
I
LOAD
= 3A, 2.2V < V
IN
< 6V
ENABLE Pin = 0.2V, V
IN
= 5V
ENABLE Pin = 0.2V, V
IN
= 6V
I
LOAD
= 3A, V
OUT
= 2.5V, 10 LD 3x3 DFN
I
LOAD
= 2A, V
OUT
= 2.5V, 10 LD 3x3 DFN
Feedback Input Current
Ground Pin Current
Ground Pin Current in
Shutdown
Dropout Voltage (Note 9)
4
FN6660.1
March 22, 2010
ISL80102, ISL80103
Electrical Specifications
Unless otherwise noted, all parameters are established over the following specified
conditions: V
IN
= V
OUT
+ 0.4V, V
OUT
= 1.8V, C
IN
= C
OUT
= 10µF, T
J
= +25°C, I
LOAD
= 0A
Applications must follow thermal guidelines of the package to determine worst case junction
temperature. Please refer to “Functional Description” on page 12 and Tech Brief
TB379.
Boldface limits apply over the operating temperature range, -40°C to +125°C.
Pulse load techniques used by ATE to ensure T
J
= T
A
defines established limits.
SYMBOL
ISC
TEST CONDITIONS
V
OUT
= 0V, V
OUT
+ 0.4V < V
IN
< 6V
V
OUT
= 0V, V
OUT
+ 0.4V < V
IN
< 6V
TSD
TSDn
V
OUT
+ 0.4V < V
IN
< 6V
V
OUT
+ 0.4V < V
IN
< 6V
MIN
MAX
(Note 8) TYP (Note 8) UNITS
5.0
2.8
160
15
A
A
°C
°C
PARAMETER
Output Short Circuit Current
(3A Version)
Output Short Circuit Current
(2A Version)
Thermal Shutdown
Temperature
Thermal Shutdown
Hysteresis (Rising Threshold)
AC CHARACTERISTICS
Input Supply Ripple
Rejection
Output Noise Voltage
PSRR
f = 1kHz, I
LOAD
= 1A; V
IN
= 2.2V
f = 120Hz, I
LOAD
= 1A; V
IN
= 2.2V
I
LOAD
= 10mA, BW = 300Hz < f < 300kHz
55
62
100
dB
µV
RMS
0.95
V
mV
µs
1
µA
ENABLE PIN CHARACTERISTICS
Turn-on Threshold
Hysteresis (Rising Threshold)
Enable Pin Turn-on Delay
Enable Pin Leakage Current
SOFT-START CHARACTERISTICS
Reset Pull-Down resistance
Soft Start Charge Current
PG PIN CHARACTERISTICS
V
OUT
PG Flag Threshold
V
OUT
PG Flag Hysteresis
PG Flag Low Voltage
PG Flag Leakage Current
NOTES:
8. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established
by characterization and are not production tested.
9. Dropout is defined by the difference in supply V
IN
and V
OUT
when the supply produces a 2% drop in V
OUT
from its nominal
value.
10. Electromigration specification defined as lifetime average junction temperature of +110°C where max rated DC current =
lifetime average current.
11. Minimum cap of 10µF X5R/X7R on V
IN
and V
OUT
required for stability.
12. If the current limit for in-rush current is acceptable in application, do not use this feature. Used only when large bulk capacitance
required on V
OUT
for application.
I
SINK
= 500µA
V
IN
= 6V, PG = 6V
75
84
4
47
0.05
100
1
92
%V
OUT
%
mV
µA
R
PD
I
CHG
-7
323
-4.5
-2
Ω
µA
V
EN(HIGH)
V
EN(HYS)
t
EN
2.2V < V
IN
< 6V
2.2V < V
IN
< 6V
C
OUT
= 10µF, I
LOAD
= 1A
V
IN
= 6V, EN = 3V
0.3
0.8
135
150
5
FN6660.1
March 22, 2010
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