To all our customers
Regarding the change of names mentioned in the document, such as
Hitachi Electric and Hitachi XX, to Renesas Technology Corp.
The semiconductor operations of Mitsubishi Electric and Hitachi were
transferred to Renesas Technology Corporation on April 1st 2003.
These operations include microcomputer, logic, analog and discrete devices,
and memory chips other than DRAMs (flash memory, SRAMs etc.)
Accordingly, although Hitachi, Hitachi, Ltd., Hitachi Semiconductors,
and other Hitachi brand names are mentioned in the document, these names
have in fact all been changed to Renesas Technology Corp.
Thank you for your understanding. Except for our corporate trademark,
logo and corporate statement, no changes whatsoever have been made to the
contents of the document, and these changes do not constitute any alteration
to the contents of the document itself.
Renesas Technology Home Page: www.renesas.com
Renesas Technology Corp.
Customer Support Dept.
April 1, 2003
Renesas Technology Corp.
Hitachi Single-Chip Microcomputer
H8/3039 Series
H8/3039, H8/3038
H8/3037, H8/3036
H8/3039 F-ZTAT
TM
Hardware Manual
ADE-602-131A
Rev. 2.0
1/12/98
Hitachi,Ltd
Preface
The H8/3039 Series comprises high-performance single-chip microcomputers (MCUs) that
integrate system supporting functions together with an H8/300H CPU core.
The H8/300H CPU has a 32-bit internal architecture with sixteen 16-bit general registers, and a
concise, optimized instruction set designed for speed. It can address a 16-Mbyte linear address
space.
The on-chip system supporting functions include ROM, RAM, a 16-bit integrated timer unit
(ITU), a programmable timing pattern controller (TPC), a watchdog timer (WDT), a serial
communication interface (SCI), an A/D converter, I/O ports, and other facilities. Of the two SCI
channels, one has been expanded to support the ISO/IEC 7816-3 smart card interface. Functions
have also been added to reduce power consumption in battery-powered applications: individual
modules can be placed in standby, and the frequency of the system clock supplied to the chip can
be divided down under software control.
The five MCU operating modes offer a choice of expanded mode, single-chip mode, and address
space size, enabling the H8/3039 Series to adapt quickly and flexibly to a variety of conditions.
In addition to its masked-ROM versions, the H8/3039 Series has an F-ZTAT
TM
* version with user
programmable on-chip flash memory that can be programmed on-board. These versions enable
users to respond quickly and flexibly to changing application specifications.
This manual describes the H8/3039 Series hardware. For details of the instruction set, refer to the
H8/300H Series Programming Manual.
Contents
Section 1
1.1
1.2
1.3
Overview
...........................................................................................................
1.4
Overview............................................................................................................................
Block Diagram...................................................................................................................
Pin Description ..................................................................................................................
1.3.1 Pin Arrangement ..................................................................................................
1.3.2 Pin Functions........................................................................................................
Pin Functions .....................................................................................................................
1
1
5
6
6
7
11
Section 2
2.1
CPU
..................................................................................................................... 15
15
15
16
17
18
19
19
20
21
22
23
23
24
26
26
27
29
39
40
40
40
43
47
47
48
48
50
51
51
52
i
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
Overview............................................................................................................................
2.1.1 Features ................................................................................................................
2.1.2 Differences from H8/300 CPU.............................................................................
CPU Operating Modes ......................................................................................................
Address Space....................................................................................................................
Register Configuration ......................................................................................................
2.4.1 Overview ..............................................................................................................
2.4.2 General Registers..................................................................................................
2.4.3 Control Registers..................................................................................................
2.4.4 Initial CPU Register Values .................................................................................
Data Formats......................................................................................................................
2.5.1 General Register Data Formats ............................................................................
2.5.2 Memory Data Formats..........................................................................................
Instruction Set....................................................................................................................
2.6.1 Instruction Set Overview......................................................................................
2.6.2 Instructions and Addressing Modes .....................................................................
2.6.3 Tables of Instructions Classified by Function......................................................
2.6.4 Basic Instruction Formats.....................................................................................
2.6.5 Notes on Use of Bit Manipulation Instructions....................................................
Addressing Modes and Effective Address Calculation .....................................................
2.7.1 Addressing Modes................................................................................................
2.7.2 Effective Address Calculation..............................................................................
Processing States ...............................................................................................................
2.8.1 Overview ..............................................................................................................
2.8.2 Program Execution State......................................................................................
2.8.3 Exception-Handling State ....................................................................................
2.8.4 Exception-Handling Sequences............................................................................
2.8.5 Reset State ............................................................................................................
2.8.6 Power-Down State................................................................................................
Basic Operational Timing..................................................................................................
2.9.1
2.9.2
2.9.3
2.9.4
Overview ..............................................................................................................
On-Chip Memory Access Timing ........................................................................
On-Chip Supporting Module Access Timing.......................................................
Access to External Address Space .......................................................................
52
52
53
54
Section 3
3.1
MCU Operating Modes
............................................................................... 55
3.2
3.3
3.4
3.5
3.6
3.7
Overview............................................................................................................................ 55
3.1.1 Operating Mode Selection.................................................................................... 55
3.1.2 Register Configuration ......................................................................................... 56
Mode Control Register (MDCR) ....................................................................................... 57
System Control Register (SYSCR).................................................................................... 58
Operating Mode Descriptions............................................................................................ 60
3.4.1 Mode 1.................................................................................................................. 60
3.4.2 Mode 3.................................................................................................................. 60
3.4.3 Mode 5.................................................................................................................. 60
3.4.4 Mode 6.................................................................................................................. 60
3.4.5 Mode 7.................................................................................................................. 60
Pin Functions in Each Operating Mode............................................................................. 61
Memory Map in Each Operating Mode............................................................................. 61
Restrictions on Use of Mode 6 .......................................................................................... 70
Section 4
4.1
Exception Handling
...................................................................................... 73
73
73
73
74
76
76
76
78
78
79
79
80
4.2
4.3
4.4
4.5
4.6
Overview............................................................................................................................
4.1.1 Exception Handling Types and Priority ...............................................................
4.1.2 Exception Handling Operation .............................................................................
4.1.3 Exception Vector Table........................................................................................
Reset ..................................................................................................................................
4.2.1 Overview ..............................................................................................................
4.2.2 Reset Sequence.....................................................................................................
4.2.3 Interrupts after Reset ............................................................................................
Interrupts............................................................................................................................
Trap Instruction .................................................................................................................
Stack Status after Exception Handling ..............................................................................
Notes on Stack Usage........................................................................................................
Section 5
5.1
Interrupt Controller
....................................................................................... 81
5.2
ii
Overview............................................................................................................................ 81
5.1.1 Features ................................................................................................................ 81
5.1.2 Block Diagram...................................................................................................... 82
5.1.3 Pin Configuration ................................................................................................. 83
5.1.4 Register Configuration ......................................................................................... 83
Register Descriptions......................................................................................................... 84
5.2.1 System Control Register (SYSCR) ...................................................................... 84
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