SN74LS160A
BCD DECADE COUNTERS/
4-BIT BINARY COUNTERS
The LS160A/161A /162A /163A are high-speed 4-bit synchronous
counters. They are edge-triggered, synchronously presettable, and
cascadable MSI building blocks for counting, memory addressing,
frequency division and other applications. The LS160A and LS162A
count modulo 10 (BCD). The LS161A and LS163A count modulo 16
(binary).
The LS160A and LS161A have an asynchronous Master Reset
(Clear) input that overrides, and is independent of, the clock and all
other control inputs. The LS162A and LS163A have a Synchronous
Reset (Clear) input that overrides all other control inputs, but is active
only during the rising clock edge.
BCD (Modulo 10)
Asynchronous Reset
Synchronous Reset
LS160A
LS162A
Binary (Modulo 16)
LS161A
LS163A
16
1
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BCD DECADE COUNTERS/
4-BIT BINARY COUNTERS
LOW POWER SCHOTTKY
J SUFFIX
CERAMIC
CASE 620-09
•
•
•
•
•
•
Synchronous Counting and Loading
Two Count Enable Inputs for High Speed Synchronous Expansion
Terminal Count Fully Decoded
Edge-Triggered Operation
Typical Count Rate of 35 MHz
ESD > 3500 Volts
CONNECTION DIAGRAM DIP
(TOP VIEW)
16
1
N SUFFIX
PLASTIC
CASE 648-08
V
CC
16
TC
15
Q
0
14
Q
1
13
Q
2
12
Q
3
11
CET
10
PE
9
NOTE:
The Flatpak version
has the same pinouts (Connection
Diagram) as the Dual In-Line Pack-
age.
16
1
D SUFFIX
SOIC
CASE 751B-03
ORDERING INFORMATION
SN54LSXXXJ
SN74LSXXXN
SN74LSXXXD
Ceramic
Plastic
SOIC
*MR for LS160A and LS161A
*SR for LS162A and LS163A
1
*R
2
CP
3
P
0
4
P
1
5
P
2
6
P
3
8
7
CEP GND
LOADING
(Note a)
HIGH
LOW
0.5 U.L.
0.25 U.L.
0.25 U.L.
0.5 U.L.
0.25 U.L.
0.25 U.L.
0.5 U.L.
5 (2.5) U.L.
5 (2.5) U.L.
7
10
2
LOGIC SYMBOL
9
3
4
5
6
PIN NAMES
PE
P
0
−P
3
CEP
CET
CP
MR
SR
Q
0
−Q
3
TC
Parallel Enable (Active LOW) Input
Parallel Inputs
Count Enable Parallel Input
Count Enable Trickle Input
Clock (Active HIGH Going Edge) Input
Master Reset (Active LOW) Input
Synchronous Reset (Active LOW) Input
Parallel Outputs (Note b)
Terminal Count Output (Note b)
1.0 U.L.
0.5 U.L.
0.5 U.L.
1.0 U.L.
0.5 U.L.
0.5 U.L.
1.0 U.L.
10 U.L.
10 U.L.
PE P
0
P
1
P
2
P
3
CEP
CET
CP
TC
15
*R Q
0
Q
1
Q
2
Q
3
1 14 13 12 11
V
CC
= PIN 16
GND = PIN 8
*MR for LS160A and LS161A
*SR for LS162A and LS163A
NOTES:
a) 1 TTL Unit Load (U.L.) = 40
μA
HIGH/1.6 mA LOW.
b) The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74)
Temperature Ranges.
©
Semiconductor Components Industries, LLC, 2006
June, 2006
−
Rev. 7
1
Publication Order Number:
MC74HC14A/D
SN74LS160A
STATE DIAGRAM
LS160A
•
LS162A
0
1
2
3
4
0
LS161A
•
LS163A
LOGIC EQUATIONS
1
2
3
4
15
5
15
5
Count Enable = CEP
w
CET
w
PE
TC for LS160A & LS162A = CET
w
Q
0
w
Q
1
w
Q
2
w
Q
3
TC for LS161A & LS163A = CET
w
Q
0
w
Q
1
w
Q
2
w
Q
3
Preset = PE
w
CP + (rising clock edge)
Reset = MR (LS160A & LS161A)
Reset = SR
w
CP + (rising clock edge)
Reset =
(LS162A & LS163A)
14
6
14
6
13
7
13
7
NOTE:
The LS160A and LS162A can be preset to any state, but will not count
beyond 9. If preset to state 10, 11, 12, 13, 14, or 15, it will return to its
normal sequence within two clock pulses.
12
11
10
9
8
12
11
10
9
8
FUNCTIONAL DESCRIPTION
The LS160A / 161A / 162A / 163A are 4-bit synchronous
counters with a synchronous Parallel Enable (Load) feature.
The counters consist of four edge-triggered D flip-flops with
the appropriate data routing networks feeding the D inputs.
All changes of the Q outputs (except due to the
asynchronous Master Reset in the LS160A and LS161A)
occur as a result of, and synchronous with, the LOW to HIGH
transition of the Clock input (CP). As long as the set-up time
requirements are met, there are no special timing or activity
constraints on any of the mode control or data inputs.
Three control inputs — Parallel Enable (PE), Count Enable
Parallel (CEP) and Count Enable Trickle (CET) — select the
mode of operation as shown in the tables below. The Count
Mode is enabled when the CEP, CET, and PE inputs are
HIGH. When the PE is LOW, the counters will synchronously
load the data from the parallel inputs into the flip-flops on the
LOW to HIGH transition of the clock. Either the CEP or CET
can be used to inhibit the count sequence. With the PE held
HIGH, a LOW on either the CEP or CET inputs at least one
set-up time prior to the LOW to HIGH clock transition will
cause the existing output states to be retained. The AND
feature of the two Count Enable inputs (CET
•
CEP) allows
synchronous cascading without external gating and without
delay accumulation over any practical number of bits or
digits.
The Terminal Count (TC) output is HIGH when the Count
Enable Trickle (CET) input is HIGH while the counter is in its
maximum count state (HLLH for the BCD counters, HHHH
MODE SELECT TABLE
*SR
L
H
H
H
H
PE
X
L
H
H
H
CET
X
X
H
L
X
CEP
X
X
H
X
L
Action on the Rising Clock Edge (
)
for the Binary counters). Note that TC is fully decoded and
will, therefore, be HIGH only for one count state.
The LS160A and LS162A count modulo 10 following a
binary coded decimal (BCD) sequence. They generate a TC
output when the CET input is HIGH while the counter is in
state 9 (HLLH). From this state they increment to state 0
(LLLL). If loaded with a code in excess of 9 they return to their
legitimate sequence within two counts, as explained in the
state diagram. States 10 through 15 do
not
generate a TC
output.
The LS161A and LS163A count modulo 16 following a
binary sequence. They generate a TC when the CET input is
HIGH while the counter is in state 15 (HHHH). From this state
they increment to state 0 (LLLL).
The Master Reset (MR) of the LS160A and LS161A is
asynchronous. When the MR is LOW, it overrides all other
input conditions and sets the outputs LOW. The MR pin
should never be left open. If not used, the MR pin should be
tied through a resistor to V
CC
, or to a gate output which is
permanently set to a HIGH logic level.
The active LOW Synchronous Reset (SR) input of the
LS162A and LS163A acts as an edge-triggered control input,
overriding CET, CEP and PE, and resetting the four counter
flip-flops on the LOW to HIGH transition of the clock. This
simplifies the design from race-free logic controlled reset
circuits, e.g., to reset the counter synchronously after
reaching a predetermined value.
RESET (Clear)
LOAD (P
n
→
Q
n
)
COUNT (Increment)
NO CHANGE (Hold)
NO CHANGE (Hold)
*For the LS162A and
*LS163A
only.
H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
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2
SN74LS160A
DEFINITION OF TERMS
SETUP TIME (t
s
) — is defined as the minimum time required
for the correct logic level to be present at the logic input prior
to the clock transition from LOW to HIGH in order to be
recognized and transferred to the outputs.
HOLD TIME (t
h
) — is defined as the minimum time following
the clock transition from LOW to HIGH that the logic level
must be maintained at the input in order to ensure continued
recognition. A negative HOLD TIME indicates that the
correct logic level may be released prior to the clock
transition from LOW to HIGH and still be recognized.
RECOVERY TIME (t
rec
) — is defined as the minimum time
required between the end of the reset pulse and the clock
transition from LOW to HIGH in order to recognize and
transfer HIGH Data to the Q outputs.
AC WAVEFORMS
t
W
t
rec
CP
Q
0
V
Q
1
V
Q
2
V
Q
3
Other conditions:
PE = L
P
0
= P
1
= P
2
= P
3
= H
t
W
(H)
CP
Q
1.3 V
t
PHL
1.3 V
t
W
(L)
1.3 V
t
PLH
1.3 V
Other conditions:
PE = MR (SR) = H
CEP = CET = H
MR
1.3 V
1.3 V
t
PHL
1.3 V
Figure 1. Clock to Output Delays, Count Frequency, and Clock Pulse Width
Figure 2. Master Reset to Output Delay, Master Reset
Pulse Width, and Master Reset Recovery Time
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