IDT74SSTVM16859
13-BIT TO 26-BIT REGISTERED BUFFER WITH SSTL I/O
COMMERCIAL TEMPERATURE RANGE
13-BIT TO 26-BIT REGISTERED
IDT74SSTVM16859
BUFFER WITH SSTL I/O
FEATURES:
•
•
•
•
•
•
•
•
1:2 register buffer
Meets or exceeds JEDEC standard SSTVM16859
2.3V to 2.7V Operation
SSTL_2 Class II style data inputs/outputs
Differential CLK input
RESET
control compatible with LVCMOS levels
Latch-up performance exceeds 100mA
ESD >2000V per MIL-STD-883, Method 3015; >200V using
machine model (C = 200pF, R = 0)
• Available in 56 pin VFQFPN and 64 pin TSSOP packages
The SSTVM16859 is a 13-bit to 26-bit registered buffer designed for
2.3V-2.7V V
DD
and supports low standby operation. All data inputs and
outputs are SSTL_2 level compatible with JEDEC standard for SSTL_2.
RESET
is an LVCMOS input since it must operate predictably during the
power-up phase.
RESET,
which can be operated independent of CLK and
CLK,
must be held in the low state during power-up in order to ensure
predictable outputs (low state) before a stable clock has been applied.
RESET,
when in the low state, will disable all input receivers, reset all
registers, and force all outputs to a low state, before a stable clock has been
applied. With inputs held low and a stable clock applied, outputs will remain
low during the Low-to-High transition of
RESET.
DESCRIPTION:
APPLICATIONS:
• Along with CSPT857C, Zero Delay PLL Clock buffer, provides
complete solution for DDR1 registered DIMMs
FUNCTIONAL BLOCK DIAGRAM
RESET
51
CLK
CLK
48
49
V
REF
D
1
45
35
1D
C1
R
32
Q
1B
16
Q
1A
TO 12 OTHER CHANNELS
COMMERCIAL TEMPERATURE RANGE
1
c
2003 Integrated Device Technology, Inc.
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
JUNE 2003
DSC-6378/4
IDT74SSTVM16859
13-BIT TO 26-BIT REGISTERED BUFFER WITH SSTL I/O
COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATIONS
Q
13A
V
DDQ
V
DDQ
GND
Q
13A
V
DDQ
Q
10A
Q
11A
Q
12A
56 Q
8A
V
DD
Q
9A
D
13
D
12
43 D
11
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
V
DDQ
GND
D
13
D
12
V
DD
V
DDQ
GND
D
11
D
10
D
9
GND
D
8
D
7
RESET
GND
CLK
CLK
V
DDQ
V
DD
V
REF
D
6
GND
D
5
D
4
D
3
GND
V
DDQ
V
DD
D
2
D
1
GND
V
DDQ
Q
12A
Q
11A
Q
10A
Q
9A
Q
7A
Q
6A
Q
5A
Q
4A
Q
3A
Q
2A
Q
1A
Q
13B
V
DDQ
Q
12B
Q
11B
Q
10B
Q
9B
1
42 D
10
D
9
D
8
D
7
RESET
GND
GND
V
DDQ
GND
Q
8A
Q
7A
Q
6A
Q
5A
Q
4A
Q
3A
Q
2A
GND
Q
1A
Q
13B
V
DDQ
Q
12B
CLK
CLK
V
DDQ
V
DD
V
REF
D
6
D
5
29 D
4
Q
8B
14
Q
7B
15
D
3
28
Q
11B
Q
10B
Q
9B
Q
8B
V
DDQ
V
DDQ
VFQFPN
TOP VIEW
V
DDQ
Q
6B
Q
5B
Q
4B
Q
3B
Q
2B
Q
1B
V
DD
D
1
D
2
Q
7B
Q
6B
GND
V
DDQ
Q
5B
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
DD
or V
DDQ
V
I
(2)
(3)
Q
4B
Description
Supply Voltage Range
Input Voltage Range
Output Voltage Range
Input Clamp Current, V
I
< 0
Output Clamp Current,
V
O
< 0 or V
O
> V
DDQ
Continuous Output Current,
V
O
= 0 to V
DDQ
Continuous Current through each
V
DD
, V
DDQ
or GND
Storage Temperature Range
Max.
–0.5 to 3.6
–0.5 to V
DD
+0.5
–0.5 to V
DDQ
+0.5
–50
±50
±50
±100
–65 to +150
Unit
V
V
V
mA
mA
mA
mA
RESET
°C
H
H
H
L
Q
3B
Q
2B
Q
1B
V
O
I
IK
I
OK
I
O
V
DD
T
STG
TSSOP
TOP VIEW
FUNCTION TABLE
(1)
Input
CLK
↑
↑
L or H
X
CLK
↓
↓
L or H
X
D
L
H
X
X
Q Outputs
L
H
Qo
(2)
L
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. The input and output negative voltage ratings may be exceeded if the ratings of the
I/P and O/P clamp current are observed.
3. The output current will flow if the following conditions are observed:
a) Output in HIGH state
b) V
O
= V
DDQ
NOTES:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
↑
= LOW to HIGH
↓
= HIGH to LOW
2. Qo = Output level before the indicated steady-state conditions were established.
2
IDT74SSTVM16859
13-BIT TO 26-BIT REGISTERED BUFFER WITH SSTL I/O
COMMERCIAL TEMPERATURE RANGE
PIN DESCRIPTION
Pin Names
Q
1
- Q
13
GND
V
DDQ
V
DD
RESET
V
REF
CLK
CLK
D
1
- D
13
Center PAD
Description
Data Output
Ground
Output-stage drain power voltage
Logic power voltage
Asynchronous reset input - resets registers and disables data and clock differential input recievers
Input reference voltage
Positive master clock input
Negative master clock input
Data Input - clocked in on the crossing of the rising edge of CLK and the falling edge of
CLK
Ground (MLF package only)
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Operating Condition: T
A
= 0°C to +70°C, V
DD
= 2.5V ±0.2V, V
DDQ
= 2.5V ±0.2V
Symbol
V
IK
V
OH
V
OL
I
I
I
DD
All Inputs
Static Standby
Static Operating
Dynamic Operating (Clock Only)
I
DDD
Dynamic Operating
(Per Each Data Input)
r
OH
r
OL
r
O(∆)
C
I
Output HIGH
Output LOW
| r
OH
- r
OL
| each separate bit
Data Inputs
CLK and
CLK
RESET
(1)
Parameter
Control Inputs
Test Conditions
V
DD
= 2.3V, I
I
=
−18mA
V
DD
= 2.3V to 2.7V, I
OH
= -100µA
V
DD
= 2.3V, I
OH
= -16mA
V
DD
= 2.3V to 2.7V, I
OL
= 100µA
V
DD
= 2.3V, I
OL
= 16mA
V
DD
= 2.7V,VI = V
DD
or GND
I
O
= 0, V
DD
= 2.7V,
RESET
= GND
I
O
= 0, V
DD
= 2.7V,
RESET
= V
DD
, V
I
= V
IH (AC)
or V
IL (AC)
I
O
= 0, V
DD
= 2.7V,
RESET
= V
DD
, V
I
= V
IH (AC)
or V
IL (AC)
,
CLK and
CLK
Switching 50% Duty Cycle.
I
O
= 0, V
DD
= 2.7V,
RESET
= V
DD
, V
I
= V
IH (AC)
or V
IL (AC)
,
CLK and
CLK
Switching 50% Duty Cycle. One Data Input
Switching at Half Clock Frequency, 50% Duty Cycle.
V
DD
= 2.3V to 2.7V, I
OH
= -20mA
V
DD
= 2.3V to 2.7V, I
OH
= 20mA
V
DD
= 2.5V, T
A
= 25°C, I
OH
= -20mA
V
DD
= 2.5V, V
I
= V
REF
±
310mV
V
ICR
= 1.25V, V
I (PP)
= 360mV
V
I
= V
DD
or GND
Min.
—
V
DD
– 0.2
1.95
—
—
—
—
—
—
—
Typ.
—
—
—
—
—
—
—
—
6
43
Max.
–1.2
—
—
0.2
0.35
±5
0.01
20
—
—
Unit
V
V
V
µA
mA
µA/Clock
MHz
µA/Clock
MHz/Data
Input
7
7
—
2
2
2
—
—
—
—
—
—
20
20
4
3
3
3
Ω
Ω
Ω
pF
NOTE:
1. Power dissipation levels will allow operation at DDR333 speeds without excessive die temperature.
3
IDT74SSTVM16859
13-BIT TO 26-BIT REGISTERED BUFFER WITH SSTL I/O
COMMERCIAL TEMPERATURE RANGE
OPERATING CHARACTERISTICS, T
A
= 25ºC
(1)
Symbol
V
DD
V
DDQ
V
REF
V
TT
V
I
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
ICR
V
I (PP)
I
OH
I
OL
T
A
NOTE:
1.
The
RESET
input of the device must be held at V
DD
or GND to ensure proper device operation.
Parameter
Supply Voltage
Output Supply Voltage
Reference Voltage (V
REF
= V
DDQ
/2)
Termination Voltage
Input Voltage
AC High-Level Input Voltage
AC Low-Level Input Voltage
DC High-Level Input Voltage
DC Low-Level Input Voltage
High-Level Input Voltage
Low-Level Input Voltage
Common-Mode Input Range
Peak-to-Peak Input Voltage
High-Level Output Current
Low-Level Output Current
Operating Free-Air Temperature
Data Inputs
Data Inputs
Data Inputs
Data Inputs
RESET
RESET
CLK,
CLK
CLK,
CLK
Min.
V
DDQ
2.3
1.15
V
REF
– 40mV
0
V
REF
+ 310mV
—
V
REF
+ 150mV
—
1.7
—
0.97
360
—
—
0
Typ.
(1)
—
2.5
1.25
V
REF
—
—
—
—
—
—
—
—
—
—
—
—
Max.
2.7
2.7
1.35
V
REF
+ 40mV
V
DD
—
V
REF
– 310mV
—
V
REF
– 150mV
—
0.7
1.53
—
– 20
20
+70
Unit
V
V
V
V
V
V
V
V
V
V
V
V
mV
mA
°C
TIMING REQUIREMENTS OVER RECOMMENDED OPERATING FREE-AIR
TEMPERATURE RANGE
V
DD
= 2.5V
±
0.2V
Symbol
CLOCK
Parameter
Clock Frequency
Pulse Duration, CLK,
CLK
HIGH or LOW
Differential Inputs Active Time
(1)
Differential Inputs Inactive Time
Setup Time, Fast Slew Rate
(2)
(3, 5)
Min.
—
2.5
—
—
Data Before CLK↑, CLK↓
Data Before CLK↑, CLK
↓
0.65
0.75
0.75
0.9
Max.
200
—
22
22
—
—
—
—
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
tw
t
ACT
t
INACT
t
SU
t
H
Setup Time, Slow Slew Rate
(4, 5)
Hold Time, Fast Slew Rate
(3,5)
Hold Time, Slow Slew Rate
(2,5)
NOTES:
1. Data inputs must be low a minimum time of t
ACT
max., after
RESET
is taken HIGH.
2. Data and clock inputs must be held at valid levels (not floating) a minimum time of t
INACT
max., after
RESET
is taken LOW.
3. For data signal input slew rate is
≥1V/ns.
4. For data signal input slew rate is
≥0.5V/ns
and <1V/ns.
5. CLK,
CLK
signal input slew rates are
≥1V/ns.
SWITCHING CHARACTERISTICS OVER RECOMMENDED FREE-AIR OPERATING
RANGE (UNLESS OTHERWISE NOTED)
V
DD
= 2.5V ± 0.2V
Symbol
f
MAX
t
PDM
t
PDMSS
t
PHL
Parameter
CLK and
CLK
to Q
CLK and
CLK
to Q (simultaneous switching)
RESET
to Q
Min.
200
1.1
—
—
Max.
—
2.6
2.9
5
Unit
MHz
ns
ns
ns
4
IDT74SSTVM16859
13-BIT TO 26-BIT REGISTERED BUFFER WITH SSTL I/O
COMMERCIAL TEMPERATURE RANGE
TEST CIRCUITS AND WAVEFORMS (V
DD
= 2.5V ± 0.2V)
V
TT
R
L
= 50Ω
From Output
Under Test
Test Point
C
L
= 30 pF
(see note 1)
Load Circuit
LVCMOS
RESET
Input
t
INACT
I
DD
(see note 2)
V
DD
V
DD
/2
V
DD
/2
t
ACT
10%
90%
0V
Timing
Input
t
PLH
Output
V
ICR
V
ICR
t
PHL
V
I(PP)
V
OH
V
TT
V
TT
V
OL
Voltage and Current Waveforms
Inputs Active and Inactive Times
Voltage Waveforms - Propagation Delay Times
LVCMOS
RESET
Input
t
W
V
IH
Input
V
REF
V
REF
Output
V
IL
V
IH
V
DD
/2
V
IL
t
PHL
V
OH
V
TT
V
OL
Voltage Waveforms - Pulse Duration
Voltage Waveforms - Propagation Delay Times
Timing
Input
t
SU
Input
V
REF
V
ICR
V
I(PP)
t
H
V
IH
V
REF
V
IL
Voltage Waveforms - Setup and Hold Times
NOTES:
1. C
L
includes probe and jig capacitance.
2. I
DD
tested with clock and data inputs held at V
DD
or GND, and I
O
= 0mA.
3. All input pulses are supplied by generators having the following characteristics: PRR
≤10MHz,
Z
O
= 50Ω, input slew rate = 1 V/ns ±20% (unless otherwise specified).
4. The outputs are measured one at a time with one transition per measurement.
5. V
TT
= V
REF
= V
DDQ
/2
6. V
IH
= V
REF
+ 310mV (AC voltage levels) for differential inputs. V
IH
= V
DD
for LVCMOS input.
7. V
IL
= V
REF
- 310mV (AC voltage levels) for differential inputs. V
IL
= GND for LVCMOS input.
8. t
PDM
is t
PD
with one output switching. t
PDMSS
is t
PD
with all outputs switching.
5
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