IA64250
Histogram/Hough Transform Processor
FEATURES
•
•
•
•
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Data Sheet
As of Production Ver. 01
Histogram and Hough Transform Calculation
Four 512 X 9 Look-up Tables Provided to Perform User-defined Point-wise
Transformations
Real-time Histogram Equalization
High Data Rates
512 X 24 Accumulation RAM
Pixel Location Function
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The IA64250 is a "plug-and-play" drop-in replacement for the original LSI® L64250. This replacement IC
has been developed using innovASIC’s MILES
TM
, or Managed IC Lifetime Extension System, cloning
technology. This technology produces replacement ICs far more complex than "emulation" while ensuring
they are compatible with the original IC. MILES
TM
captures the design of a clone so it can be produced even
as silicon technology advances. MILES
TM
also verifies the clone against the original IC so that even the
"undocumented features" are duplicated. This data sheet documents all necessary engineering information
about the IA64250 including functional and I/O descriptions, electrical characteristics, and applicable timing.
Package Pinout for 68 PLCC PACKAGE:
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
8
7
6
5
4
3
2
1
68
67
66
65 64 63 62 61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
28 29 30 31 32 33
34 35
36 37 38 39 40
41
42 43
Copyright
©
2000
ENG211001219-01
innovASIC
The End of Obsolescence™
Page 1 of 21
www.innovasic.com
Customer Support:
1-888-824-4184
IA64250
Histogram/Hough Transform Processor
Description
Data Sheet
As of Production Ver. 01
The IA64250 performs three separate tasks, histogram generation, modified Hough transforms, and
pixel location. There are three modes of operation for the IA64250: computation, I/O, and
initialization.
The controller block in the block diagram decodes the instructions and contains the mode registers.
After decoding the mode, the controller generates all of the control signals to the rest of the part.
These control signals include the addresses and input data for the LUT and ACC RAMs, the select
lines for both the output mux and the shifter, and the reset for the FP counter. This block also
controls the clearing of the ACC RAM.
The ACC RAM stores the video data that is to be output during the I/O mode. This data can be
modified, depending on mode, by several methods prior to being output. These methods are
described in the computation mode section.
The LUT RAM can store up to four different data modifying functions. These functions are used to
modify the video data coming in and access the appropriate data in the ACC RAM through the ACC
RAM address. This data is then sent out on the DO output.
During the initialization mode, the functions to be performed are defined. This is accomplished by
setting the values in the mode registers contained in the controller block.
During the computation mode, the histogram, Hough transform, or pixel location data is computed.
Data equalization also occurs during this mode if desired. The controller block controls the adders
and shifters during this mode to ensure correct data manipulation. This is accomplished through the
data stored in the mode registers as well as the DV input. The controller block also generates the
addresses to both the RAMs.
The I/O mode allows data to be transferred to the Accumulation RAM (ACC RAM) and/or to and
from the Look Up Table RAM (LUT RAM). The user can also update the marker memory during
the I/O mode. The marker memory is used to quickly find points of interest on the histogram,
Hough transform, or accumulated histogram curves. Up to seven points of interest can be specified
on the grey level axis or parameter axis. The corresponding value on the accumulation axis will then
be available. The reverse is also true, where the user can specify accumulation values of interest and
obtain the corresponding grey values. The memory map located in the I/O mode description shows
the configuration of the data stored in the memory. The transfer of data from an external source to
either of the RAMs is done through either the CI or DI input bus. The controller block takes in the
data and passes it along to the appropriate RAM. The controller block also supplies the RAM with
the address and control signals needed to write the data. During a data transfer from one RAM to
the other, the controller block performs a similar task, overseeing the transfer and supplying the
necessary control signals and address.
Copyright
©
2000
ENG211001219-01
innovASIC
The End of Obsolescence™
Page 4 of 21
www.innovasic.com
Customer Support:
1-888-824-4184
IA64250
Histogram/Hough Transform Processor
I/O SIGNAL DESCRIPTION:
Data Sheet
As of Production Ver. 01
The diagram below describes the I/O characteristics for each signal on the IC. The signal
names correspond to the signal names on the pinout diagrams provide.
I/O Characteristics:
IODV
VDO.0 - VDO.8
CIO.0 - CIO.8
W
E
REGADR.0 - REGADR.5
AT
CLK1
CLK2
STARTIO
CX,CY
RX,RY
RESET FP
PO
O
O
I
I
I
I
I
I
I
I
I
I
O
When HIGH, ACC RAM or LUT RAM data on the DO bus is valid.
LUT RAM data output (uses CLK1).
Control register and LUT input data bus.
Used to strobe data into mode latches when LOW.
Selects mode latch, marker or maximum registers.
Selects marker and maximum registers when HIGH or mode latches when LOW.
AT must be LOW to access the LUT or ACC RAMs via the DO bus.
Pixel clock active at rising edge.
User I/O clock (may be connected to CLK1)
Initiates RAM I/O at HIGH to LOW transition.
Used to increment X or Y counters when HIGH.
Resets X or Y counters(overrides CX, CY) when HIGH.
Resets FP counter when HIGH.
Test pin should be left unconnected.
Copyright
©
2000
ENG211001219-01
innovASIC
The End of Obsolescence™
Page 5 of 21
www.innovasic.com
Customer Support:
1-888-824-4184
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