Integrated Device Technology, Inc.
FAST CMOS
SYNCHRONOUS
PRESETTABLE
BINARY COUNTERS
DESCRIPTION:
IDT54/74FCT161T/AT/CT
IDT54/74FCT163T/AT/CT
FEATURES:
•
•
•
•
Std., A and C speed grades
Low input and output leakage
≤1µA
(max.)
CMOS power levels
True TTL input and output compatibility
– V
OH
= 3.3V (typ.)
– V
OL
= 0.3V (typ.)
High drive outputs (-15mA I
OH
, 48mA I
OL
)
Meets or exceeds JEDEC standard 18 specifications
Product available in Radiation Tolerant and Radiation
Enhanced versions
Military product compliant to MIL-STD-883, Class B
and DESC listed (dual marked)
Available in DIP, SOIC, QSOP, CERPACK and LCC
packages
•
•
•
•
•
The IDT54/74FCT161T/163T, IDT54/74FCT161AT/ 163AT
and IDT54/74FCT161CT/163CT are high-speed synchro-
nous modulo-16 binary counters built using an advanced dual
metal CMOS technology. They are synchronously preset-
table for application in programmable dividers and have two
types of count enable inputs plus a terminal count output for
versatility in forming synchronous multi-stage counters. The
IDT54/74FCT161T/AT/CT have asynchronous Master Reset
inputs that override all other inputs and force the outputs LOW.
The IDT54/74FCT163T/AT/CT have Synchronous Reset in-
puts that override counting and parallel loading and allow the
outputs to be simultaneously reset on the rising edge of the
clock.
FUNCTIONAL BLOCK DIAGRAMS
P
0
PE
'161 '163
CEP
CET
163
ONLY
TC
P
1
P
2
P
3
CP
CP
161
ONLY
CP
D CP D
C
D
Q Q
Q
0
Q
0
DETAIL A
MR ('161)
SR ('163)
Q
0
Q
1
Q
2
Q
3
2611 drw 01
DETAIL
A
DETAIL
A
DETAIL
A
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1995
Integrated Device Technology, Inc.
OCTOBER 1994
DSC-4219/4
6.7
1
IDT54/74FCT161T/AT/CT, IDT54/74FCT163T/AT/CT
FAST CMOS SYNCHRONOUS PRESETTABLE BINARY COUNTERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
IDT54/74FCT861 10-BIT TRANSCEIVERS
*R
CP
P
0
P
1
P
2
P
3
CEP
GND
1
2
3
4
5
6
7
8
16
INDEX
P16-1,
D16-1,
S016-1,
S016-7
&
E16-1
15
14
13
12
11
10
9
CEP
GND
NC
PE
CET
Vcc
TC
Q
0
Q
1
Q
2
Q
3
CET
PE
2611 drw 02
CP
*R
NC
Vcc
TC
3
2
4
5
6
7
8
20 19
18
1
17
16
15
14
9 10 11 12 13
P
0
P
1
NC
P
2
P
3
L20-2
Q
0
Q
1
NC
Q
2
Q
3
2611 drw 03
*
MR
for '161
*
SR
for ‘163
DIP/SOIC/QSOP/CERPACK
TOP VIEW
LCC
TOP VIEW
PIN DESCRIPTION
Pin Names
CEP
CET
CP
Description
Count Enable Parallel Input
Count Enable Trickle Input
Clock Pulse Input (Active Rising Edge)
Asynchronous Master Reset Input (Active LOW)
Synchronous Reset Input (Active LOW)
Parallel Data Inputs
Parallel Enable Input (Active LOW)
Flip-Flop Outputs
Terminal Count Output
2611 tbl 01
FUNCTION TABLE
(2)
SR
(1)
L
H
H
H
H
PE
X
L
H
H
H
CET
X
X
H
L
X
CEP
X
X
H
X
L
Action on the Rising
Clock Edge(s)
Reset (Clear)
Load (P
n
→Q
n
)
Count (Increment)
No Change (Hold)
No Change (Hold)
MR
(‘161)
SR
(‘163)
P
0-3
PE
Q
0-3
TC
2611 tbl 02
NOTES:
1. 163 only.
2. H = HIGH Voltage Level, L = LOW Voltage Level, X = Don’t Care.
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
Rating
Commercial
V
TERM(2)
Terminal Voltage
–0.5 to +7.0
with Respect to
GND
V
TERM(3)
Terminal Voltage
–0.5 to
with Respect to
V
CC
+0.5
GND
T
A
Operating
0 to +70
Temperature
T
BIAS
Temperature
–55 to +125
Under Bias
T
STG
Storage
–55 to +125
Temperature
P
T
Power Dissipation
0.5
I
OUT
DC Output
Current
–60 to +120
Military
–0.5 to +7.0
Unit
V
CAPACITANCE
(T
A
= +25°C, f = 1.0MHz)
Symbol
Parameter
(1)
C
IN
Input
Capacitance
C
OUT
Output
Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
Typ.
6
8
Max. Unit
10
pF
12
pF
2611 lnk 04
–0.5 to
V
CC
+0.5
–55 to +125
–65 to +135
–65 to +150
0.5
–60 to +120
V
°C
°C
°C
W
mA
NOTE:
1. This parameter is measured at characterization but not tested.
2611 lnk 03
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT-
INGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other condi-
tions above those indicated in the operational sections of this specifica-
tion is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability. No terminal voltage may exceed
V
CC
by +0.5V unless otherwise noted.
2. Input and V
CC
terminals only.
3. Outputs and I/O terminals only.
6.7
2
IDT54/74FCT161T/AT/CT, IDT54/74FCT163T/AT/CT
FAST CMOS SYNCHRONOUS PRESETTABLE BINARY COUNTERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Commercial: T
A
= 0°C to +70°C, V
CC
= 5.0V
±
5%; Military: T
A
= –55°C to +125°C, V
CC
= 5.0V
±
10%
Symbol
V
IH
V
IL
I
IH
I
IL
I
I
V
IK
I
OS
V
OH
Parameter
Input HIGH Level
Input LOW Level
Input HIGH Current
(4)
Input LOW Current
(4)
Input HIGH Current
(4)
Clamp Diode Voltage
Short Circuit Current
Output HIGH Voltage
Test Conditions
(1)
Guaranteed Logic HIGH Level
Guaranteed Logic LOW Level
V
CC
= Max.
V
CC
= Max.
V
CC
= Max., V
I
= V
CC
(Max.)
V
CC
= Min., I
N
= –18mA
V
CC
= Max.
(3)
, V
O
= GND
V
CC
= Min.
V
IN
= V
IH
or V
IL
I
OH
= –6mA MIL.
I
OH
= –8mA COM’L.
I
OH
= –12mA MIL.
I
OH
= –15mA COM’L.
V
OL
V
H
I
CC
Output LOW Voltage
Input Hysteresis
Quiescent Power
Supply Current
V
CC
= Max.
V
IN
= GND or V
CC
V
CC
= Min.
V
IN
= V
IH
or V
IL
—
I
OL
= 32mA MIL.
I
OL
= 48mA COM’L.
V
I
= 2.7V
V
I
= 0.5V
COM'L
MIL
(5)
Min.
2.0V
2.7V
—
—
—
—
—
–60
2.4
2.0
—
—
—
Typ.
(2)
—
—
—
—
—
—
–0.7
–120
3.3
3.0
0.3
200
0.01
Max.
—
—
0.8
±1
±1
±1
–1.2
–225
—
—
0.5
—
1
Unit
V
V
V
µA
µA
µA
V
mA
V
V
V
mV
mA
2611 tbl 05
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 5.0V, +25°C ambient.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. The test limit for this parameter is
±5µA
at T
A
= -55°C.
5. Clock pin requires a minimum V
IH
of 2.5V.
6.7
3
IDT54/74FCT161T/AT/CT, IDT54/74FCT163T/AT/CT
FAST CMOS SYNCHRONOUS PRESETTABLE BINARY COUNTERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
Symbol
∆I
CC
I
CCD
Parameter
Quiescent Power Supply Current
TTL Inputs HIGH
Dynamic Power Supply Current
(4)
Test Conditions
(1)
V
CC
= Max.
V
IN
= 3.4V
(3)
V
CC
= Max., Outputs Open
Load Mode
CEP = CET =
PE
= GND
MR
or
SR
= V
CC
One Input Toggling
50% Duty Cycle
V
CC
= Max., Outputs Open
Load Mode
f
CP
= 10MHz
50% Duty Cycle
CEP = CET =
PE
= GND
MR
or
SR
= V
CC
One Bit Toggling
at f
i
= 5MHz
50% Duty Cycle
V
CC
= Max., Outputs Open
Load Mode
f
CP
= 10MHz
50% Duty Cycle
CEP = CET =
PE
= GND
MR
or
SR
= V
CC
Four Bits Toggling
at f
i
= 5MHz
50% Duty Cycle
V
IN
= V
CC
V
IN
= GND
Min.
—
—
Typ.
(2)
0.5
0.15
Max.
2.0
0.25
Unit
mA
mA/
MHz
I
C
Total Power Supply Current
(6)
V
IN
= V
CC
V
IN
= GND
—
1.5
3.5
mA
V
IN
= 3.4V
V
IN
= GND
—
2.0
5.5
V
IN
= V
CC
V
IN
= GND
—
3.8
7.3
(5)
V
IN
= 3.4V
V
IN
= GND
—
5.0
12.3
(5)
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 5.0V, +25°C ambient.
3. Per TTL driven input (V
IN
= 3.4V). All other inputs at V
CC
or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the I
CC
formula. These limits are guaranteed but not tested.
6. I
C
= I
QUIESCENT
+ I
INPUTS
+ I
DYNAMIC
I
C
= I
CC
+
∆I
CC
D
H
N
T
+ I
CCD
(f
CP/
2 + f
i
N
i
)
I
CC
= Quiescent Current
∆I
CC
= Power Supply Current for a TTL High Input (V
IN
= 3.4V)
D
H
= Duty Cycle for TTL Inputs High
N
T
= Number of TTL Inputs at D
H
I
CCD
= Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
f
CP
= Clock Frequency for Register Devices (Zero for Non-Register Devices)
f
i
= Input Frequency
N
i
= Number of Inputs at f
i
All currents are in milliamps and all frequencies are in megahertz.
2611 tbl 06
6.7
4
IDT54/74FCT161T/AT/CT, IDT54/74FCT163T/AT/CT
FAST CMOS SYNCHRONOUS PRESETTABLE BINARY COUNTERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
IDT54/74FCT161T
IDT54/74FCT163T
Com'l.
Symbol
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PHL
t
PHL
t
SU
Parameter
Propagation Delay
CP to Q
n
(
PE
Input HIGH)
Propagation Delay
CP to Q
n
(
PE
Input LOW)
Propagation Delay
CP to TC
Propagation Delay
CET to TC
Propagation Delay
MR
to Q
n
('161)
Propagation Delay
MR
to TC ('161)
Set-up Time,
HIGH or LOW
P
n
to CP
Hold Time,
HIGH or LOW
P
n
to CP
Set-up Time,
HIGH or LOW
PE
or
SR
to CP
Hold Time,
HIGH or LOW
PE
or
SR
to CP
Set-up Time,
HIGH or LOW
CEP or CET to CP
Hold Time,
HIGH or LOW
CEP or CET to CP
Clock Pulse
Width (Load)
HIGH or LOW
Clock Pulse
Width (Count)
HIGH or LOW
Condition
(1)
C
L
= 50pF
R
L
= 500Ω
2.0
11.0
2.0
Mil.
11.5
IDT54/74FCT161AT
IDT54/74FCT163AT
Com'l.
2.0
7.2
2.0
Mil.
7.5
IDT54/74FCT161CT
IDT54/74FCT163CT
Com'l
2.0
5.8
2.0
Mil.
Unit
ns
6.3
Min.
(2)
Max. Min.
(2)
Max. Min.
(2)
Max. Min.
(2)
Max. Min.
(2)
Max. Min.
(2)
Max.
2.0
9.5
2.0
10.0
2.0
6.2
2.0
6.5
2.0
5.8
2.0
6.3
ns
2.0
1.5
2.0
2.0
5.0
15.0
8.5
13.0
11.5
—
2.0
1.5
2.0
2.0
5.5
16.5
9.0
14.0
12.5
—
2.0
1.5
2.0
2.0
4.0
9.8
5.5
8.5
7.5
—
2.0
1.5
2.0
2.0
4.5
10.8
5.9
9.1
8.2
—
2.0
1.5
2.0
2.0
4.0
7.4
5.2
6.0
7.0
—
2.0
1.5
2.0
2.0
4.5
8.3
5.6
6.6
7.7
—
ns
ns
ns
ns
ns
t
H
1.5
—
2.0
—
1.5
—
2.0
—
1.5
—
2.0
—
ns
t
SU
11.5
—
13.5
—
9.5
—
11.5
—
9.5
—
11.5
—
ns
t
H
1.5
—
1.5
—
1.5
—
1.5
—
1.5
—
1.5
—
ns
t
SU
11.5
—
13.0
—
9.5
—
11.0
—
9.5
—
11.0
—
ns
t
H
0
—
0
—
0
—
0
—
0
—
0
—
ns
t
W
5.0
—
5.0
—
4.0
(3)
—
4.0
(3)
—
4.0
(3)
—
4.0
(3)
—
ns
t
W
7.0
—
8.0
—
6.0
—
7.0
—
6.0
—
7.0
—
ns
t
W
t
REM
MR
Pulse Width,
LOW ('161)
Recovery Time
MR
to CP ('161)
5.0
6.0
—
—
5.0
6.0
—
—
4.0
(3)
5.0
—
—
4.0
(3)
5.0
—
—
4.0
(3)
5.0
—
—
4.0
(3)
5.0
—
—
ns
ns
NOTES:
1. See test circuits and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. This limit is guaranteed but not tested.
2611 tbl 07
6.7
5
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