74LVC3G34-Q100
Triple buffer
Rev. 1 — 16 May 2013
Product data sheet
1. General description
The 74LVC3G34-Q100 provides three buffers.
The inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of
the 74LVC3G34-Q100 as a translator in a mixed 3.3 V and 5 V environment.
This device is fully specified for partial power-down applications using I
OFF
. The I
OFF
circuitry disables the output, preventing a damaging backflow current through the device
when it is powered down.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from
40 C
to +85
C
and from
40 C
to +125
C
Wide supply voltage range from 1.65 V to 5.5 V
5 V tolerant input/output for interfacing with 5 V logic
High noise immunity
Complies with JEDEC standard:
JESD8-7 (1.65 V to 1.95 V)
JESD8-5 (2.3 V to 2.7 V)
JESD8B/JESD36 (2.7 V to 3.6 V)
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0
)
24
mA output drive (V
CC
= 3.0 V)
CMOS low power consumption
Latch-up performance exceeds 250 mA
Direct interface with TTL levels
Multiple package options
NXP Semiconductors
74LVC3G34-Q100
Triple buffer
3. Ordering information
Table 1.
Ordering information
Package
Temperature range Name
74LVC3G34DP-Q100
40 C
to +125
C
74LVC3G34DC-Q100
40 C
to +125
C
TSSOP8
Description
plastic thin shrink small outline package; 8 leads;
body width 3 mm; lead length 0.5 mm
Version
SOT505-2
SOT765-1
Type number
VSSOP8 plastic very thin shrink small outline package;
8 leads; body width 2.3 mm
4. Marking
Table 2.
Marking codes
Marking code
[1]
V34
Y34
Type number
74LVC3G34DP-Q100
74LVC3G34DC-Q100
[1]
The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5. Functional diagram
1
1A
1Y
1
3Y
3A
2A
2Y
1
A
Y
001aac536
001aah842
001aah843
Fig 1.
Logic symbol
Fig 2.
IEC logic symbol
Fig 3.
Logic diagram (one gate)
74LVC3G34_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 16 May 2013
2 of 14
NXP Semiconductors
74LVC3G34-Q100
Triple buffer
6. Pinning information
6.1 Pinning
Fig 4.
Pin configuration SOT505-2 and SOT765-1
6.2 Pin description
Table 3.
Symbol
1A, 2A, 3A
1Y, 2Y, 3Y
GND
V
CC
Pin description
Pin
1, 3, 6
7, 5, 2
4
8
Description
data input
data output
ground (0 V)
supply voltage
7. Functional description
Table 4.
Input nA
L
H
[1]
H = HIGH voltage level; L = LOW voltage level.
Function table
[1]
Output nY
L
H
74LVC3G34_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 16 May 2013
3 of 14
NXP Semiconductors
74LVC3G34-Q100
Triple buffer
8. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
I
IK
V
I
I
OK
V
O
I
O
I
CC
I
GND
P
tot
T
stg
[1]
[2]
[3]
Parameter
supply voltage
input clamping current
input voltage
output clamping current
output voltage
output current
supply current
ground current
total power dissipation
storage temperature
Conditions
V
I
< 0 V
[1]
Min
0.5
50
0.5
-
[1]
[1][2]
Max
+6.5
-
+6.5
50
V
CC
+ 0.5
+6.5
50
100
-
250
+150
Unit
V
mA
V
mA
V
V
mA
mA
mA
mW
C
V
O
> V
CC
or V
O
< 0 V
Active mode
Power-down mode
V
O
= 0 V to V
CC
0.5
0.5
-
-
100
T
amb
=
40 C
to +125
C
[3]
-
65
The minimum input and output voltage ratings may be exceeded if the input and output current ratings are observed.
When V
CC
= 0 V (Power-down mode), the output voltage can be 5.5 V in normal operation.
For TSSOP8 package: above 55
C
the value of P
tot
derates linearly with 2.5 mW/K.
For VSSOP8 package: above 110
C
the value of P
tot
derates linearly with 8 mW/K.
9. Recommended operating conditions
Table 6.
Symbol
V
CC
V
I
V
O
T
amb
t/V
Operating conditions
Parameter
supply voltage
input voltage
output voltage
ambient temperature
input transition rise and fall rate
V
CC
= 1.65 V to 2.7 V
V
CC
= 2.7 V to 5.5 V
Active mode
Power-down mode; V
CC
= 0 V
Conditions
Min
1.65
0
0
0
40
-
-
Max
5.5
5.5
V
CC
5.5
+125
20
10
Unit
V
V
V
V
C
ns/V
ns/V
74LVC3G34_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 16 May 2013
4 of 14
NXP Semiconductors
74LVC3G34-Q100
Triple buffer
10. Static characteristics
Table 7.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
T
amb
=
40 C
to +85
C
V
IH
HIGH-level input voltage
V
CC
= 1.65 V to 1.95 V
V
CC
= 2.3 V to 2.7 V
V
CC
= 2.7 V to 3.6 V
V
CC
= 4.5 V to 5.5 V
V
IL
LOW-level input voltage
V
CC
= 1.65 V to 1.95 V
V
CC
= 2.3 V to 2.7 V
V
CC
= 2.7 V to 3.6 V
V
CC
= 4.5 V to 5.5 V
V
OH
HIGH-level output voltage
V
I
= V
IH
or V
IL
I
O
=
100 A;
V
CC
= 1.65 V to 5.5 V
I
O
=
4
mA; V
CC
= 1.65 V
I
O
=
8
mA; V
CC
= 2.3 V
I
O
=
12
mA; V
CC
= 2.7 V
I
O
=
24
mA; V
CC
= 3.0 V
I
O
=
32
mA; V
CC
= 4.5 V
V
OL
LOW-level output voltage
V
I
= V
IH
or V
IL
I
O
= 100
A;
V
CC
= 1.65 V to 5.5 V
I
O
= 4 mA; V
CC
= 1.65 V
I
O
= 8 mA; V
CC
= 2.3 V
I
O
= 12 mA; V
CC
= 2.7 V
I
O
= 24 mA; V
CC
= 3.0 V
I
O
= 32 mA; V
CC
= 4.5 V
I
I
I
OFF
I
CC
I
CC
C
I
input leakage current
power-off leakage current
supply current
additional supply current
input capacitance
V
I
= 5.5 V or GND; V
CC
= 0 V to 5.5 V
V
CC
= 0 V; V
I
or V
O
= 5.5 V
V
I
= 5.5 V or GND;
V
CC
= 1.65 V to 5.5 V; I
O
= 0 A
per pin; V
CC
= 2.3 V to 5.5 V;
V
I
= V
CC
0.6 V; I
O
= 0 A
V
CC
= 3.3 V; V
I
= GND to V
CC
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.1
0.1
0.1
5
2.5
0.1
0.45
0.3
0.4
0.55
0.55
5
10
10
500
-
V
V
V
V
V
V
A
A
A
A
pF
V
CC
0.1
1.2
1.9
2.2
2.3
3.8
-
-
-
-
-
-
-
-
-
-
-
-
V
V
V
V
V
V
0.65
V
CC
1.7
2.0
0.7
V
CC
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.35
V
CC
0.7
0.8
0.3
V
CC
V
V
V
V
V
V
V
V
Conditions
Min
Typ
[1]
Max
Unit
74LVC3G34_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 16 May 2013
5 of 14
FPGA/CPLD
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
