HYB39S16400/800/160BT-8/-10
16MBit Synchronous DRAM
16 MBit Synchronous DRAM
Advanced Information
•
High Performance:
-8
fCK(max.)
tCK3
tAC3
tCK2
tAC2
125
8
6
10
6
-10
100
10
7
13.3
8
Units
MHz
ns
ns
ns
ns
•
•
•
•
•
•
•
•
•
•
•
Multiple Burst Read with Single Write
Operation
Automatic
Command
and
Controlled
Precharge
Data Mask for Read / Write control (x4, x8)
Dual Data Mask for byte control ( x16)
Auto Refresh (CBR) and Self Refresh
Suspend Mode and Power Down Mode
4096 refresh cycles / 64 ms
Random Column Address every CLK
( 1-N Rule)
Single 3.3V +/- 0.3V Power Supply
LVTTL Interface
Plastic Packages:
P-TSOPI-44 400mil width ( x4, x8 )
P-TSOPII -50 400 mil width ( x 16 )
-8 version for PC100 applications
•
•
•
•
•
•
•
Fully Synchronous to Positive Clock Edge
0 to 70
°C
operating temperature
Dual Banks controlled by A11 ( Bank Select)
Programmable CAS Latency : 2, 3
Programmable Wrap Sequence : Sequential
or Interleave
Programmable Burst Length: 1, 2, 4, 8
full page(optional) for sequencial wrap
around
•
The HYB39S16400/800/160BT are dual bank Synchronous DRAM’ based on the die revisions “ “
s
D,
& “ and organized as 2 banks x 2MBit x4, 2 banks x 1MBit x8 and 2 banks x 512kbit x16
E”
respectively. These synchronous devices achieve high speed data transfer rates up to 125 MHz by
employing a chip architecture that prefetches multiple bits and then synchronizes the output data to
a system clock. The chip is fabricated with SIEMENS’advanced 16MBit DRAM process technology.
The device is designed to comply with all JEDEC standards set for synchronous DRAM products,
both electrically and mechanically. All of the control, address, data input and output circuits are
synchronized with the positive edge of an externally supplied clock.
Operating the two memory banks in an interleaved fashion allows random access operation to occur
at higher rate than is possible with standard DRAMs. A sequential and gapless data rate of up to 125
MHz is possible depending on burst length, CAS latency and speed grade of the device.
Auto Refresh (CBR) and Self Refresh operation are supported. These devices operate with a single
3.3V +/- 0.3V power supply and are available in TSOPII packages.
These Synchronous DRAM devices are available with LV-TTL interfaces.
Semiconductor Group
1
4.98
HYB39S16400/800/160BT-8/-10
16MBit Synchronous DRAM
Ordering Information
Type
Ordering Code
Package
Description
LVTTL-version:
HYB 39S16400BT-8
HYB 39S16400BT-10
HYB 39S16800BT-8
HYB 39S16800BT-10
HYB 39S16160BT-8
HYB 39S16160BT-10
P-TSOPII-44 (400mil)
P-TSOPII-44-(400mil)
P-TSOPII-44-(400mil)
P-TSOPII-44 (400mil)
P-TSOPII-50 (400mil)
P-TSOPII-50-(400mil)
125MHz 2B x 2M x 4 SDRAM
100MHz 2B x 2M x 4 SDRAM
125MHz 2B x 1M x 8 SDRAM
100MHz 2B x 1M x 8 SDRAM
125MHz 2B x 512k x 16 SDRAM
100MHz 2B x 512k x 16 SDRAM
Pin Description and Pinouts:
CLK
CKE
CS
RAS
CAS
WE
A0-A10
A11 (BS)
Clock Input
Clock Enable
Chip Select
Row Address Strobe
Column Address Strobe
Write Enable
Address Inputs
Bank Select
DQ
DQM, LDQM, UDQM
Vdd
Vss
Vddq
Vssq
NC
Data Input /Output
Data Mask
Power (+3.3V)
Ground
Power for DQ’ (+ 3.3V)
s
Ground for DQ’
s
not connected
Semiconductor Group
2
HYB39S16400/800/160BT-8/-10
16MBit Synchronous DRAM
Vdd
NC
Vssq
DQ0
Vddq
NC
Vssq
DQ1
Vddq
NC
NC
WE
CAS
RAS
CS
A11
A10
A0
A1
A2
A3
Vdd
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
Vss
NC
Vssq
DQ3
Vddq
NC
Vssq
DQ2
Vddq
NC
NC
DQM
CLK
CKE
NC
A9
A8
A7
A6
A5
A4
Vss
Vdd
DQ0
Vssq
DQ1
Vddq
DQ2
Vssq
DQ3
Vddq
NC
NC
WE
CAS
RAS
CS
A11
A10
A0
A1
A2
A3
Vdd
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
Vss
DQ7
Vssq
DQ6
Vddq
DQ5
Vssq
DQ4
Vddq
NC
NC
DQM
CLK
CKE
NC
A9
A8
A7
A6
A5
A4
Vss
HYB39S16400BT
2 Bank x 2MBit x 4
TSOPII-44
( 400 mil x 725 mil)
Vdd
DQ0
DQ1
Vssq
DQ2
DQ3
Vddq
DQ4
DQ5
Vssq
DQ6
DQ7
Vddq
LDQM
WE
CAS
RAS
CS
A11
A10
A0
A1
A2
A3
Vdd
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
Vss
DQ15
DQ14
Vssq
DQ13
DQ12
Vddq
DQ11
DQ10
Vssq
DQ9
DQ8
Vddq
NC
UDQM
CLK
CKE
NC
A9
A8
A7
A6
A5
A4
Vss
HYB39S16800BT
2 Bank x 1MBit x 8
TSOPII-44
( 400 mil x 725 mil )
HYB39S16160BT
2 Bank x 512kbit x 16
TSOPII-50
( 400 mil x 825 mil )
Semiconductor Group
3
HYB39S16400/800/160BT-8/-10
16MBit Synchronous DRAM
Signal Pin Description
Pin
CLK
Type
Input
Signal Polarity
Pulse
Function
Positive The system clock input. All of the SDRAM inputs are sampled on the rising
Edge edge of the clock.
Active
High
Active
Low
Active
Low
Activates the CLK signal when high and deactivates the CLK signal when
low, thereby inititiates either the Power Down mode, Suspend mode or the
Self Refresh mode.
CS enables the command decoder when low and disables the command
decoder when high. When the command decoder is disabled, new
commands are ignored but previous operations continue.
When sampled at the positive rising edge of the clock, CAS, RAS, and WE
define the command to be executed by the SDRAM.
During a Bank Activate command cycle, A0-A10 defines the row address
(RA0-RA10) when sampled at the rising clock edge.
During a Read or Write command cycle, A0-A9 defines the column
address (CA0-CAn) when sampled at the rising clock edge.CAn depends
from the SDRAM organisation.
4M x 4 SDRAM CAn = CA9
2M x 8 SDRAM CAn = CA8
1M x 16 SDRAM CAn = CA7
In addition to the column address, A10 is used to invoke autoprecharge
operation at the end of the burst read or write cycle. If A10 is high,
autoprecharge is selected and A11 defines the bank to be precharged
(low=bank A, high=bank B). If A10 is low, autoprecharge is disabled.
During a Precharge command cycle, A10 is used in conjunction with A11
to control which bank(s) to precharge. If A10 is high, both bank A and bank
B will be precharged regardless of the state of A11. If A10 is low, then A11
is used to define which bank to precharge.
CKE
Input
Level
CS
RAS,
CAS
WE
Input
Pulse
Input
Pulse
A0 -
A10
Input
Level
—
A11
(BS)
DQx
Input
Input
Output
Level
Level
—
—
Selects which bank is to be active. A11 low selects bank A and A11 high
selects bank B.
Data Input/Output pins operate in the same manner as on conventional
DRAMs.
The Data Input/Output mask places the DQ buffers in a high impedance
state when sampled high. In Read mode, DQM has a latency of two clock
cycles and controls the output buffers like an output enable. In Write
mode, DQM has a latency of zero and operates as a word mask by
allowing input data to be written if it is low but blocks the write operation if
DQM is high.
Power and ground for the input buffers and the core logic.
DQM
LDQM
UDQM
Input
Pulse
Active
High
VDD,
VSS
VDDQ
VSSQ
Supply
Supply
—
—
Isolated power supply and ground for the output buffers to provide
improved noise immunity.
Semiconductor Group
4
HYB39S16400/800/160BT-8/-10
16MBit Synchronous DRAM
Row Decoder
2048
2048 x 1024
Memory Bank A
CKE
CKE Buffer
Self
Refresh Clock
1024
Row
Address
Counter
Bank A
Row/Column
Select
Predecode A
3
Sequential
Control
Bank A
Sense Amplifiers
Column Decoder and DQ Gate
4
11
8
Data Latches
Data Input/Output Buffers
CLK
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11 (BS)
CLK Buffer
Address Buffers (12)
12
8
12
11
Mode Register
8
Sequential
Control
3
Bank B
11
Predecode B
Bank B
Row/Column
Select
DQ0
DQ1
DQ2
DQ3
CS
CS Buffer
Data Latches
8
RAS Buffer
Command Decoder
RAS
Column Decoder and DQ Gate
Sense Amplifiers
1024
2048
Row Decoder
2048
Memory Bank B
2048 x 1024
CAS
CAS Buffer
WE
DQM
WE Buffer
DQM Buffer
Block Diagram for HYB39S16400BT (2 banks x 4M x 4 SDRAM)
Semiconductor Group
5
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
