UM10430
LPC18xx ARM Cortex-M3 microcontroller
Rev. 3.0 — 26 July 2017
User manual
Document information
Info
Keywords
Content
LPC18xx, LPC1850, LPC1830, LPC1820, LPC1810, LPC185x, LPC183x,
LPC182x, LPC181x, LPC18Sxx, LPC18S50, LPC18S30, LPC18S20,
LPC18S10, LPC18S5x, LPC18S3x, LPC18S2x, LPC18S1x, ARM Cortex-M3,
SPIFI, SCT, USB, Ethernet, LPC1800, LPC1800 User manual
LPC18xx user manual
Abstract
NXP Semiconductors
UM10430
LPC18xx User manual
Revision history
Rev
3.0
Modifications:
Date
20170726
Description
LPC18xx user manual
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Updated
Section 12.2.1.1 “Changing the BASE_M3_CLK after power-up, reset, or deep power-down
mode”.
Added list item 4.
Updated
Section 12.2.1.2 “Changing the BASE_M3_CLK after waking up from deep-sleep or
power-down modes”.
Added list item 3.
Updated
Table 114 “PLL0USB control register (PLL0USB_CTRL, address 0x4005 0020) bit
description”.
Added table note to AUTOBLOCK, bit 11.
Updated
Table 118 “PLL0AUDIO control register (PLL0AUDIO_CTRL, address 0x4005 0030) bit
description”.
Added table note to AUTOBLOCK, bit 11.
Updated
Table 123 “PLL1_CTRL register (PLL1_CTRL, address 0x4005 0044) bit description”.
Added table note to AUTOBLOCK, bit 11.
LPC18xx user manual
2.9
Modifications:
20170118
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Fixed formatting issues.
Updated Table 19 “QSPI devices supported by the boot code and the SPIFI API”:
Deleted Table: QSPI devices not supported by the boot code.
LPC18xx user manual
2.8
Modifications:
20151210
Fixed formatting issues.
Added CREG1 register. See Table 90 “CREG1 register (CREG1, address 0x4004 3008) bit
description”.
Updated text in Section 12.2.1 “Configuring the BASE_M3_CLK for high operating frequencies”: To
ramp up the clock frequency to an operating frequency above 110 MHz configure the core clock
BASE_M4_CLK as described in Section 12.2.1.1.
Updated description for USB0 (Event 9) and USB1(Event 10) peripheral in Table 75 “Event router
inputs”; USB0: Wake-up request signal. Not active in power-down and deep power-down mode. Use
for wake-up from sleep and deep-sleep mode; USB1: USB1 AHB_NEED_CLK signal. Not active in
power-down and deep power-down mode. Use for wake up from sleep and deep-sleep mode.
Updated Table 170 “LPC1850/30/20/10 Pin description (flashless parts)”: Fixed PD_3 to be "SCT
Output 6"; was SCT Output 7.
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UM10430
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2017. All rights reserved.
User manual
Rev. 3.0 — 26 July 2017
2 of 1284
NXP Semiconductors
UM10430
LPC18xx User manual
Revision history
…continued
Rev
2.7
Modifications:
Date
20151104
Description
LPC18xx user manual
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Added S parts to Table 1 “Ordering information”, Table 2 “Ordering options (flashless parts)”, Table 3
“Ordering information (parts with on-chip flash)”, and Table 4 “Ordering options (parts with on-chip
flash)”.
Added 16 kB EEPROM in Section 1.2 “Features”.
Added the line to the remark in Section 10.4.10 “USB0 frame length adjust register” and
Section 10.4.11 “USB1 frame length adjust register”: This register should be read before the
initialization of USB0 and USB1.
Fixed typographical error in Section 6.2 “Features”: Cipher-Block chaining.
Added the paragraph: The Motor control PWM is not available on LPC1810FET100,
LPC1820FET100, and LPC1830FET100 parts to Section 31.1 “How to read this chapter”.
Added 0x10 to all the offsets for exception numbers 53 and above ending with 0x110 for the QEI
vector. See Table 72 “Connection of interrupt sources to the NVIC”.
Added device and hex coding information for S parts to Table 40 “LPC18xx part identification
numbers”.
Fixed CBC to read Cipher Block Chaining instead of Cipher Book Chaining in Section 8.2 “Features”.
Updated Section 28.6 “Register description”text. Was REGMODEn = 1: Registers operate as match
and reload registers. REGMODEn = 0: Registers operate as capture and capture control registers. 0
and 1 reversed to read, REGMODEn = 0: Registers operate as match and reload registers.
REGMODEn = 1: Registers operate as capture and capture control registers.
Updated Section 29.3 “Register description” text. Was REGMODEn = 1: Registers operate as match
and reload registers. REGMODEn = 0: Registers operate as capture and capture control registers. 0
and 1 reversed to read, REGMODEn = 0: Registers operate as match and reload registers.
REGMODEn = 1: Registers operate as capture and capture control registers.
Fixed references to LPC18xx in List item 5 on page 97 and Section 7.3.4 “CMAC”: For LPC18xx the
chosen CMAC parameters are: encryption key K = User Key (AES key1, same as used for
decryption) and tag length l = 64.
Updated Table 18 “Boot image header description”: Reserved bits: 15:8 instead of 15:14.
Updated Table 69 “Boot image header description”: AES_CONTROL bits: 15:8. added a remark
before the table.
In Table 103 “Power-down modes register (PD0_SLEEP0_MODE - address 0x4004 201C) bit
description” “Power-down modes register (PD0_SLEEP0_MODE - address 0x4004 201C) bit
description”, the value of Deep power down mode is changed to 0x0033 FF7F.
In Table 14 “OTP function allocation”, updated otp_ProgUSBID: otp_ProgUSBID will program prod_id
and vend_id in word 1 of bank 3: 3; word 1.
Re-named Part ID register to CHIP ID register: Table 88 “Register overview: Configuration registers
(base address 0x4004 3000)” and Table 97 “Chip ID register (CHIPID, address 0x4004 3200) bit
description”. Added CHIP ID for Flash devices Rev A: CHIP ID is 0x7906 002B to
Table 97.
Added SBUSCFG register. See Table 384 “System bus interface configuration register (SBUSCFG -
address 0x4000 6090) bit description”. Added a remark in Section 23.6.10 “Burst Size register
(BURSTSIZE)”.
Updated Figure 21 “IAP parameter passing”.
Changed the IAP command array size to 5: See Section 5.8 “IAP commands”.
Define data structure or pointers to pass the IAP command table and result table to the IAP function:
unsigned long command[5]; unsigned long result[5];
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UM10430
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2017. All rights reserved.
User manual
Rev. 3.0 — 26 July 2017
3 of 1284
NXP Semiconductors
UM10430
LPC18xx User manual
Revision history
…continued
Rev
Modifications:
Date
Description
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Updated Table 48 “IAP Copy RAM to Flash command”.
Added a bullet to Section 5.2 “Basic configuration”. If the application uses the IAP interface, it must
reserve the SRAM space used by IAP as outlined in Section 5.4.5.8 “RAM used by IAP command
handler”.
Updated Section 5.4.5.8 “RAM used by IAP command handler”. Added text: 16 B of RAM from
0x10089FF0 to 0x10089FFF. Applications making use of IAP calls must reserve this RAM block.
Updated Section 5.4.5.7 “RAM used by ISP”; removed command handler from the title and updated
text.
Updated Figure 27 “Boot flow for encrypted images (flashless parts)”.
Updated Figure 32 “AES endianness”.
LPC18xx user manual
2.6
Modifications:
20150210
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Table 700 “SCT configuration example” corrected.
Number of EMC_CS and EMC_DYCS pins corrected for the LQFP208 pin package in Table 343
“EMC pinout for different packages”.
Section 38.7.5.1 “USART clock in synchronous mode” added.
Bit 12 changed to 1 for EMC address mapping 256 Mb, 512 Mb, 1 Gb. See Table 367 “Address
mapping”.
Bit description of bits TSEG1 and TSEG2 corrected in Table 976 “CAN bit timing register (BT,
address 0x400E 200C (C_CAN0) and 0x400A 400C (C_CAN1)) bit description” and Figure 172 “Bit
timing” updated for clarification.
Parts MX1635E, W25Q16DV, W25Q32FV added to Table 19 “QSPI devices supported by the boot
code and the SPIFI API”.
Use of IAP calls clarified: IAP commands are not supported for flash-less parts. See Section 5.8 “IAP
commands”.
For flashless parts only: Unique part ID is stored in OTP bank 0, word 2 and readable at memory
location 0x4004 5008. See Section 3.1 and Table 9 “OTP memory description (OTP base address
0x4004 5000)”.
For secure parts only: Chapter 7 “LPC18xx Boot ROM for secure parts” added.
For secure parts only: AES DMA request lines added. See Table 92, Table 252, and Table 272.
Boot ROM chapter split into two chapters for secure and non-secure parts. See Chapter 4 “LPC18xx
Boot ROM” and Chapter 7 “LPC18xx Boot ROM for secure parts”.
Description of USB0_DM and USB1_DM pins corrected: These pins do not contain an internal
pull-up. See Table 381 and Table 443.
Section 4.1.1 “Determine the boot code version” added.
UM10430
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2017. All rights reserved.
User manual
Rev. 3.0 — 26 July 2017
4 of 1284
NXP Semiconductors
UM10430
LPC18xx User manual
Revision history
…continued
Rev
Modifications:
Date
Description
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Signal polarity of signals EMC_CKEOUT and EMC_DQMOUT corrected in Table 346 “EMC pin
description”. Both signals are active HIGH.
Corrected remark for bits MODE3, RFCLK, and FBCLK in Table 335 “SPIFI control register (CTRL,
address 0x4000 3000) bit description”: MODE3, RFCLK, and FBCLK should not all be 1, because in
this case there is no final falling edge on SCK on which to sample the last data bit of the frame.
Bit 4 changed from Reserved to SEE (System Error Enable) in register USBINTR_D and
USBINTR_H . See Table 395 and Table 396.
Bit 4 changed from Reserved to SEI in register USBSTS_D and USBSTS_H. See Table 393 and
Table 394.
Bit 4 changed from Reserved to SEE (System Error Enable) register USBINTR_D and USBINTR_H.
See Table 456 and Table 457.
Bit 4 changed from Reserved to SEI register USBSTS_D and USBSTS_H. See Table 454 and
Table 455.
Added Section 23.11, System error.
Removed BUS_RST from Table 153.
Added a remark on how to read the FLADJ register in Section 10.4.10 and Section 10.4.11.
Added text: The USART3 boot mode is not supported for LPC18Sxx parts. See Section 4.1, Table 15,
Table 16, and Section 7.1
UM10430
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2017. All rights reserved.
User manual
Rev. 3.0 — 26 July 2017
5 of 1284
Microchip MCU
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