16 MBit Synchronous DRAM
(second generation)
Advanced Information
• High Performance:
CAS latency = 3
-8
125
8
7
-10
100
10
8
Units
MHz
ns
ns
HYB 39S16400/800/160AT-8/-10
• Multiple Burst Read with Single Write
Operation
• Automatic and Controlled Precharge
Command
• Data Mask for Read/Write control (× 4,
×
8)
• Dual Data Mask for byte control (× 16)
• Auto Refresh (CBR) and Self Refresh
• Suspend Mode and Power Down Mode
• 4096 refresh cycles/64 ms
• Random Column Address every CLK
(1-N Rule)
• Single 3.3 V
±
0.3 V Power Supply
• LVTTL Interface versions
• Plastic Packages:
P-TSOPII-44-1 400 mil width (× 4,
×
8)
P-TSOPII-50-1 400 mil width (× 16)
f
CK
t
CK3
t
AC3
• Single Pulsed RAS Interface
• Fully Synchronous to Positive Clock Edge
• 0 to 70
°C
operating temperature
• Dual Banks controlled by A11 (Bank Select)
• Programmable CAS Latency: 1, 2, 3
• Programmable Wrap Sequence: Sequential
or Interleave
• Programmable Burst Length:
1, 2, 4, 8 and full page for Sequential type
1, 2, 4, 8 for Interleave type
The HYB 39S1640x/80x/16xAT are dual bank Synchronous DRAM’s based on the die revisions “B”
and “C” and organized as 2 banks
×
2 MBit
×
4, 2 banks
×
1 MBit
×
8 and 2 banks
×
512 kBit
×
16
respectively. These synchronous devices achieve high speed data transfer rates up to 125 MHz by
employing a chip architecture that prefetches multiple bits and then synchronizes the output data to
a system clock. The chip is fabricated with SIEMENS advanced 16 MBit DRAM process technology.
The device is designed to comply with all JEDEC standards set for synchronous DRAM products,
both electrically and mechanically. All of the control, address, data input and output circuits are
synchronized with the positive edge of an externally supplied clock.
Operating the two memory banks in an interleaved fashion allows random access operation to occur
at higher rate than is possible with standard DRAMs. A sequential and gapless data rate of up to
125 MHz is possible depending on burst length, CAS latency and speed grade of the device.
Auto Refresh (CBR) and Self Refresh operation are supported. These devices operate with a single
3.3 V
±
0.3 V power supply and are available in TSOPII packages.
Semiconductor Group
1
1998-10-01
HYB 39S16400/800/160AT-8/-10
16 MBit Synchronous DRAM
Ordering Information
Type
LVTTL-Version
HYB 39S16400AT-8 Q67100-Q1333 P-TSOPII-44-1 (400 mil) 125 MHz 2B
×
2 M
×
4 SDRAM
PC66 2-2-2
HYB 39S16400AT-10 Q67100-Q1323 P-TSOPII-44-1 (400 mil) 100 MHz 2B
×
2 M
×
4 SDRAM
PC66 2-2-2
HYB 39S16800AT-8 Q67100-Q1335 P-TSOPII-44-1 (400 mil) 125 MHz 2B
×
1 M
×
8 SDRAM
PC66 2-2-2
HYB 39S16800AT-10 Q67100-Q1327 P-TSOPII-44-1 (400 mil) 100 MHz 2B
×
1 M
×
8 SDRAM
PC66 2-2-2
HYB 39S16160AT-8 Q67100-Q1337 P-TSOPII-50-1 (400 mil) 125 MHz 2B
×
512 k
×
16 SDRAM
HYB 39S16160AT-10 Q67100-Q1331 P-TSOPII-50-1 (400 mil) 100 MHz 2B
×
512 k
×
16 SDRAM
Pin Names
CLK
CKE
CS
RAS
CAS
WE
A0 - A10
A11 (BS)
Clock Input
Clock Enable
Chip Select
Row Address Strobe
Column Address Strobe
Write Enable
Address Inputs
Bank Select
DQ
DQM, LDQM,
UDQM
Data Input/Output
Data Mask
Power (+ 3.3 V)
Ground
Power for DQ’s (+ 3.3 V)
Ground for DQ’s
Not connected
Ordering Code Package
Description
V
DD
V
SS
V
DDQ
V
SSQ
NC
Semiconductor Group
2
1998-10-01
HYB 39S16400/800/160AT-8/-10
16 MBit Synchronous DRAM
V
DD
DQ0
V
SSQ
DQ1
V
DDQ
DQ2
V
SSQ
DQ3
V
DDQ
N.C.
N.C.
WE
CAS
RAS
CS
A11
A10
A0
A1
A2
A3
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
SPP03402
V
SS
DQ7
V
SSQ
DQ6
V
DDQ
DQ5
V
SSQ
DQ4
V
DDQ
N.C.
N.C.
DQM
CLK
CKE
N.C.
A9
A8
A7
A6
A5
A4
V
SS
Pin Configuration
Semiconductor Group
3
1998-10-01
HYB 39S16400/800/160AT-8/-10
16 MBit Synchronous DRAM
Signal Pin Description
Pin
CLK
CKE
Type
Input
Input
Signal Polarity Function
Pulse
Level
Positive
Edge
Active
High
Active
Low
The system clock input. All of the SDRAM inputs are
sampled on the rising edge of the clock.
Activates the CLK signal when high and deactivates the
CLK signal when low, thereby initiates either the Power
Down mode, Suspend mode or the Self Refresh mode.
CS enables the command decoder when low and disables
the command decoder when high. When the command
decoder is disabled, new commands are ignored but
previous operations continue.
When sampled at the positive rising edge of the clock,
CAS, RAS and WE define the command to be executed by
the SDRAM.
During a Bank Activate command cycle, A0 - A10 defines
the row address (RA0 - RA10) when sampled at the rising
clock edge.
During a Read or Write command cycle, A0 - A9 defines
the column address (CA0 - CAn) when sampled at the
rising clock edge. CAn depends from the SDRAM
organisation.
4M
×
4 SDRAM CAn = CA9
2M
×
8 SDRAM CAn = CA8
1M
×
16 SDRAM CAn = CA7
In addition to the column address, A10 is used to invoke
autoprecharge operation at the end of the burst read or
write cycle. If A10 is high, autoprecharge is selected and
A11 defines the bank to be precharged (low = bank A,
high = bank B). If A10 is low, autoprecharge is disabled.
During a Precharge command cycle, A10 is used in
conjunction with A11 to control which bank(s) to
precharge. If A10 is high, both bank A and bank B will be
precharged regardless of the state of A11. If A10 is low,
then A11 is used to define which bank to precharge.
Selects which bank is to be active. A11 low selects bank A
and A11 high selects bank B.
Data Input/Output pins operate in the same manner as on
conventional DRAMs.
CS
Input
Pulse
RAS
CAS
WE
A0 - A10
Input
Pulse
Active
Low
–
Input
Level
A11 (BS)
DQx
Input
Level
–
–
Input
Level
Output
Semiconductor Group
4
1998-10-01
HYB 39S16400/800/160AT-8/-10
16 MBit Synchronous DRAM
Signal Pin Description
(cont’d)
Pin
DQM
LDQM
UDQM
Type
Input
Signal Polarity Function
Pulse
Active
High
The Data Input/Output mask places the DQ buffers in a
high impedance state when sampled high. In Read mode,
DQM has a latency of two clock cycles and controls the
output buffers like an output enable. In Write mode, DQM
has a latency of zero and operates as a word mask by
allowing input data to be written if it is low but blocks the
write operation if DQM is high.
Power and ground for the input buffers and the core logic.
Isolated power supply and ground for the output buffers to
provide improved noise immunity.
V
DD
V
SS
V
DDQ
V
SSQ
Supply –
Supply –
–
–
Semiconductor Group
5
1998-10-01
FPGA/CPLD
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