HYB39S16160CT-6/-7
16MBit Synchronous DRAM
1M x 16 MBit Synchronous DRAM
for High Speed Graphics Applications
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High Performance:
-6
fCKmax @ CL=3
tCK3
tAC3
fCKmax @ CL=2
tCK2
tAC2
166
6
5
125
8
6
-7
143
7
5.5
115
9
6
Units
MHz
ns
ns
MHz
ns
ns
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full page(optional) for sequencial wrap
around
Multiple Burst Read with Single Write
Operation
Automatic
Command
and
Controlled
Precharge
Data Mask for Read / Write control
Dual Data Mask for byte control ( x16)
Auto Refresh (CBR) and Self Refresh
Suspend Mode and Power Down Mode
4096 refresh cycles / 64 ms
Latency 2 @ 125 MHz
Latency 3 @ 166 MHz
Random Column Address every CLK
( 1-N Rule)
Single 3.3V +/- 0.3V Power Supply
LVTTL Interface
Plastic Packages:
P-TSOPII-50 400mil width ( x16 )
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Fully Synchronous to Positive Clock Edge
0 to 70
°C
operating temperature
Dual Banks controlled by A11 ( Bank Select)
Programmable CAS Latency : 2, 3
Programmable Wrap Sequence : Sequential
or Interleave
Programmable Burst Length: 1, 2, 4, 8
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The HYB39S16160CT-6/-7 are high speed dual bank Synchronous DRAM’s based on SIEMENS
0.25µm process and organized as 2 banks x 512kbit x 16. These synchronous devices achieve high
speed data transfer rates up to 166 MHz by employing a chip architecture that prefetches multiple
bits and then synchronizes the output data to a system clock. The chip is fabricated with SIEMENS’
advanced 16MBit DRAM process technology.
The device is designed to comply with all JEDEC standards set for synchronous DRAM products,
both electrically and mechanically. All of the control, address, data input and output circuits are
synchronized with the positive edge of an externally supplied clock.
Operating the two memory banks in an interleaved fashion allows random access operation to occur
at higher rate than is possible with standard DRAMs. A sequential and gapless data rate of up to 166
MHz is possible depending on burst length, CAS latency and speed grade of the device.
Auto Refresh (CBR) and Self Refresh operation are supported. These devices operate with a single
3.3V +/- 0.3V power supply and are available in TSOPII packages.
These Synchronous DRAM devices are available with LV-TTL interfaces.
Semiconductor Group
1
10.98
HYB39S16160CT-6/-7
16MBit Synchronous DRAM
Ordering Information
Type
Ordering Code
Package
Description
LVTTL-version:
HYB 39S16160CT-6
HYB 39S16160CT-7
P-TSOPII-50 (400mil)
P-TSOPII-50 (400mil)
166MHz 2B x 512k x 16 SDRAM
143MHz 2B x 512k x 16 SDRAM
Pin Description and Pinouts:
CLK
CKE
CS
RAS
CAS
WE
A0-A10
A11 (BS)
Clock Input
Clock Enable
Chip Select
Row Address Strobe
Column Address Strobe
Write Enable
Address Inputs
Bank Select
DQ
LDQM, UDQM
Vdd
Vss
Vddq
Vssq
NC
Data Input /Output
Data Mask
Power (+3.3V)
Ground
Power for DQ’s (+ 3.3V)
Ground for DQ’s
not connected
Pin-Out
Vdd
DQ0
DQ1
Vssq
DQ2
DQ3
Vddq
DQ4
DQ5
Vssq
DQ6
DQ7
Vddq
LDQM
WE
CAS
RAS
CS
A11
A10
A0
A1
A2
A3
Vdd
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
Vss
DQ15
DQ14
Vssq
DQ13
DQ12
Vddq
DQ11
DQ10
Vssq
DQ9
DQ8
Vddq
NC
UDQM
CLK
CKE
NC
A9
A8
A7
A6
A5
A4
Vss
Semiconductor Group
2
HYB39S16160CT-6/-7
16MBit Synchronous DRAM
Signal Pin Description
Pin
CLK
Type
Input
Signal Polarity
Pulse
Function
Positive The system clock input. All of the SDRAM inputs are sampled on the rising
Edge edge of the clock.
Active
High
Active
Low
Active
Low
Activates the CLK signal when high and deactivates the CLK signal when
low, thereby inititiates either the Power Down mode, Suspend mode or the
Self Refresh mode.
CS enables the command decoder when low and disables the command
decoder when high. When the command decoder is disabled, new
commands are ignored but previous operations continue.
When sampled at the positive rising edge of the clock, CAS, RAS, and WE
define the command to be executed by the SDRAM.
During a Bank Activate command cycle, A0-A10 defines the row address
(RA0-RA10) when sampled at the rising clock edge.
During a Read or Write command cycle, A0-A9 defines the column
address (CA0-CAn) when sampled at the rising clock edge.CAn depends
from the SDRAM organisation.
CKE
Input
Level
CS
RAS,
CAS
WE
Input
Pulse
Input
Pulse
A0 -
A10
1M x 16 SDRAM CAn = CA7
Input
Level
—
In addition to the column address, A10 is used to invoke autoprecharge
operation at the end of the burst read or write cycle. If A10 is high,
autoprecharge is selected and A11 defines the bank to be precharged
(low=bank A, high=bank B). If A10 is low, autoprecharge is disabled.
During a Precharge command cycle, A10 is used in conjunction with A11
to control which bank(s) to precharge. If A10 is high, both bank A and bank
B will be precharged regardless of the state of A11. If A10 is low, then A11
is used to define which bank to precharge.
A11
(BS)
DQx
Input
Input
Output
Level
Level
—
—
Selects which bank is to be active. A11 low selects bank A and A11 high
selects bank B.
Data Input/Output pins operate in the same manner as on conventional
DRAMs.
The Data Input/Output mask places the DQ buffers in a high impedance
state when sampled high. In Read mode, DQM has a latency of two clock
cycles and controls the output buffers like an output enable. In Write
mode, DQM has a latency of zero and operates as a word mask by
allowing input data to be written if it is low but blocks the write operation if
DQM is high.
Power and ground for the input buffers and the core logic.
LDQM,
UDQM
Input
Pulse
Active
High
VDD,
VSS
VDDQ
VSSQ
Supply
Supply
—
—
Power supply and ground for the output buffers to provide improved noise
immunity.
Semiconductor Group
3
HYB39S16160CT-6/-7
16MBit Synchronous DRAM
Row Decoder
Row Decoder
Row Decoder
Row Decoder
2048 x 512
Memory Bank A
2048 x 256
Memory Bank A
2048
1024
16
512
1024
256
CKE
CKE Buffer
Self
Refresh Clock
Row
Address
Counter
Bank A
Row/Column
Select
16
CLK
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11 (BS)
CLK Buffer
16
11 Predecode A
3
Sequential
Control
Bank A
8
8
8
Data Latches
Data Latches
Data Latches
Data Latches
16
8
8
Address Buffers (12)
12
12
11
Mode Register
8
Sequential
Control
3
Bank B
CS
CS Buffer
11 Predecode B
RAS Buffer
Command Decoder
16
Data Latches
Data Latches
8
RAS
Bank B
Row/Column
Select
16
Column Decoder and DQ Gate
Column Decoder and DQ Gate
Sense Amplifiers
256
CAS
CAS Buffer
16
Sense Amplifiers
Row Decoder
Row Decoder
Row Decoder
Row Decoder
WE
WE Buffer
2048
Memory Bank B
Memory Bank B
2048 x B
Memory Bank256
2048 x 1024
Memory Bank B
2048 x 512
2048 x 1024
UDQM
DQM Buffer
LDQM
DQM Buffer
Block Diagram for HYB39S16160CT (2 banks x 512k x 16 SDRAM)
Semiconductor Group
4
Data Input/Output Buffers
Sense Amplifiers
Sense Amplifiers
Sense Amplifiers
Column Decoder and DQ Gate
Sense Amplifiers
Column Decoder and DQ Gate
Column Decoder and DQ Gate
Column Decoder and DQ Gate
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
HYB39S16160CT-6/-7
16MBit Synchronous DRAM
Operation Definition
All of SDRAM operations are defined by states of control signals CS, RAS, CAS, WE, and DQM at
the positive edge of the clock. The following list shows the most important operation commands.
Operation
Standby, Ignore RAS, CAS, WE and Address
Row Address Strobe and Activating a Bank
Column Address Strobe and Read Command
Column Address Strobe and Write Command
Precharge Command
Burst Stop Command
Self Refresh Entry
Mode Register Set Command
Write Enable/Output Enable
Write Inhibit/Output Disable
No Operation (NOP)
CS
H
L
L
L
L
L
L
L
X
X
L
RAS
X
L
H
H
L
H
L
L
X
X
H
CAS
X
H
L
L
H
H
L
L
X
X
H
WE
X
H
H
L
L
L
H
L
X
X
H
(L/U)DQM
X
X
X
X
X
X
X
X
L
H
X
Mode Register
For application flexibility, a CAS latency, a burst length, and a burst sequence can be
programmed in the SDRAM mode register. The mode set operation must be done before any
activate command after the initial power up. Any content of the mode register can be altered by re-
executing the mode set command. Both banks must be in precharged state and CKE must be high
at least one clock before the mode set operation. After the mode register is set, a Standby or NOP
command is required. Low signals of RAS, CAS, and WE at the positive edge of the clock activate
the mode set operation. Address input data at this timing defines parameters to be set as shown in
the following table.
Semiconductor Group
5
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