HYB 39L128160AC/T
128-MBit 3.3V Mobile-RAM
128-MBit Synchronous Low-Power DRAM
Datasheet (Rev. 2003-02)
High Performance:
• Automatic and Controlled Precharge
Command
-8
125
8
6
9.5
6
Units
MHz
ns
ns
ns
ns
• Programmable Burst Length: 1, 2, 4, 8 and
full page
• Data Mask for byte control
• Auto Refresh (CBR)
• 4096 Refresh Cycles / 64ms
• Very low Self Refresh current
• Power Down and Clock Suspend Mode
-7.5
f
CK,MAX
t
CK3,MIN
t
AC3,MAX
t
CK2,MIN
t
AC2,MAX
133
7.5
5.4
9.5
6
• 8Mbit x 16 organisation
• VDD = VDDQ = 3.3V
• Fully Synchronous to Positive Clock Edge
• Four Banks controlled by BA0 & BA1
• Programmable CAS Latency: 2, 3
• Programmable Wrap Sequence: Sequential
or Interleave
• Random Column Address every CLK
(1-N Rule)
• 54-FBGA , with 9 x 6 ball array with 3
depopulated rows, 9 x 8 mm
• Operating Temperature Range
Commerical (0
0
to 70
0
C)
The HYB 39L128160AC Mobile-RAM is a new generation of low power, four bank Synchronous
DRAM organized as 4 banks
×
2Mbit x16. These synchronous Mobile-RAMs achieve high speed
data transfer rates by employing a chip architecture that prefetches multiple bits and then
synchronizes the output data to a system clock.
All of the control, address, data input and output circuits are synchronized with the positive edge of
an externally supplied clock.
Operating the four memory banks in an interleave fashion allows random access operation to occur
at higher rate. A sequential and gapless data rate is possible depending on burst length, CAS
latency and speed grade of the device.
Auto Refresh (CBR) and Self Refresh operation are supported. The device operates with a single
3.3 V
±
0.3 V power supply.
Compared to conventional SDRAM the self-refresh current is further reduced. The Mobile-RAM
devices are available in FBGA “chip-size” or TSOPII packages.
INFINEON Technologies
1
2003-02
HYB 39L128160AC/T
128-MBit 3.3V Mobile-RAM
Functional Block Diagrams
Column Addresses
A0 - A8, AP,
BA0, BA1
Row Addresses
A0 - A11,
BA0, BA1
Column Address
Counter
Column Address
Buffer
Row Address
Buffer
Refresh Counter
Row
Decoder
Row
Decoder
Row
Decoder
Row
Decoder
Column Decoder
Sense amplifier & I(O) Bus
Column Decoder
Sense amplifier & I(O) Bus
Column Decoder
Sense amplifier & I(O) Bus
Memory
Array
Memory
Array
Memory
Array
Column Decoder
Sense amplifier & I(O) Bus
Memory
Array
Bank 0
4096 x 512
x 16 Bit
Bank 1
4096 x 512
x 16 Bit
Bank 2
4096 x 512
x 16 Bit
Bank 3
4096 x 512
x 16 Bit
Input Buffer
Output Buffer
Control Logic &
Timing Generator
DQ0 - DQ15
Block Diagram: 8Mb x16 SDRAM (12 / 9 / 2 addressing)
INFINEON Technologies
5
CLK
CKE
CS
RAS
CAS
WE
DQMU
DQML
SPB04124
2003-02
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