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HD74LV4040AT

产品描述LV/LV-A/LVX/H SERIES, ASYN NEGATIVE EDGE TRIGGERED 12-BIT UP BINARY COUNTER, PDSO16, TSSOP-16
产品类别逻辑    逻辑   
文件大小179KB,共11页
制造商Renesas(瑞萨电子)
官网地址https://www.renesas.com/
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HD74LV4040AT概述

LV/LV-A/LVX/H SERIES, ASYN NEGATIVE EDGE TRIGGERED 12-BIT UP BINARY COUNTER, PDSO16, TSSOP-16

HD74LV4040AT规格参数

参数名称属性值
厂商名称Renesas(瑞萨电子)
零件包装代码TSSOP
包装说明TSSOP-16
针数16
Reach Compliance Codecompliant
计数方向UP
系列LV/LV-A/LVX/H
JESD-30 代码R-PDSO-G16
长度5 mm
负载/预设输入YES
逻辑集成电路类型BINARY COUNTER
工作模式ASYNCHRONOUS
位数12
功能数量1
端子数量16
最高工作温度85 °C
最低工作温度-40 °C
封装主体材料PLASTIC/EPOXY
封装代码TSSOP
封装形状RECTANGULAR
封装形式SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
传播延迟(tpd)22.2 ns
认证状态Not Qualified
座面最大高度1.1 mm
最大供电电压 (Vsup)5.5 V
最小供电电压 (Vsup)2 V
标称供电电压 (Vsup)2.5 V
表面贴装YES
技术CMOS
温度等级INDUSTRIAL
端子形式GULL WING
端子节距0.65 mm
端子位置DUAL
触发器类型NEGATIVE EDGE
宽度4.4 mm
最小 fmax125 MHz
Base Number Matches1

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HD74LV4040A
12-stage Binary Counter
REJ03D0337–0200Z
(Previous ADE-205-282 (Z))
Rev.2.00
Jul. 20, 2004
Description
The HD74LV4040A is a 12 stage counter. This device is incremented on the falling edge (negative transition) of the
input clock, and all its output is reset to a low level by applying a logical high on its reset input. Low-voltage and high-
speed operation is suitable for the battery-powered products (e.g., notebook computers), and the low-power
consumption extends the battery life.
Features
V
CC
= 2.0 V to 5.5 V operation
All inputs V
IH
(Max.) = 5.5 V (@V
CC
= 0 V to 5.5 V)
All outputs V
O
(Max.) = 5.5 V (@V
CC
= 0 V)
Typical V
OL
ground bounce < 0.8 V (@V
CC
= 3.3 V, Ta = 25°C)
Typical V
OH
undershoot > 2.3 V (@V
CC
= 3.3 V, Ta = 25°C)
Output current ±6 mA (@V
CC
= 3.0 V to 3.6 V), ±12 mA (@V
CC
= 4.5 V to 5.5 V)
Ordering Information
Package Type
SOP–16 pin (JEITA)
SOP–16 pin (JEDEC)
TSSOP–16 pin
Package Code
FP–16DAV
FP–16DNV
TTP–16DAV
Package
Abbreviation
FP
RP
T
Taping Abbreviation
(Quantity)
EL (2,000 pcs/reel)
EL (2,500 pcs/reel)
ELL (2,000 pcs/reel)
Part Name
HD74LV4040AFPEL
HD74LV4040ARPEL
HD74LV4040ATELL
Note: Please consult the sales office for the above package availability.
Function Table
Inputs
CLK
X
Note: H:
L:
X:
↑:
↓:
High level
Low level
Immaterial
Low to high transition
High to low transition
CLR
L
L
H
Output
Q
n
Remains unchanged
Changed
All outputs low
Rev.2.00 Jul. 20, 2004 page 1 of 10

 
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