H8/3877U Series
H8/3877U, H8/3876U, H8/3875U
Hardware Manual
Preface
The H8/300L Series of single-chip microcomputers has a high-speed H8/300L CPU core, with
many necessary peripheral system functions on-chip. The H8/300L CPU instruction set is
compatible with the H8/300 CPU.
On-chip peripheral functions of the H8/3877U Series include a high-precision DTMF generator
for tone dialing, a multitone generator, an LCD controller/driver, three types of timers, two serial
communication interface channels, and an A/D converter.
This manual describes the hardware of the H8/3877U Series. For details on the H8/3877U Series
instruction set, refer to the
H8/300L Series Programming Manual.
Contents
Section 1
1.1
1.2
1.3
Overview
.........................................................................................................
Overview.........................................................................................................................
Internal Block Diagram ..................................................................................................
Pin Arrangement and Functions .....................................................................................
1.3.1 Pin Arrangement.................................................................................................
1.3.2 Pin Functions ......................................................................................................
1
1
5
6
6
7
Section 2
2.1
CPU
................................................................................................................... 11
11
11
12
12
13
13
13
15
15
16
17
18
18
20
24
26
28
29
29
31
35
37
38
40
40
41
43
43
44
44
44
2.2
2.3
2.4
2.5
2.6
2.7
Overview.........................................................................................................................
2.1.1 Features...............................................................................................................
2.1.2 Address Space.....................................................................................................
2.1.3 Register Configuration........................................................................................
Register Descriptions......................................................................................................
2.2.1 General Registers................................................................................................
2.2.2 Control Registers ................................................................................................
2.2.3 Initial Register Values.........................................................................................
Data Formats...................................................................................................................
2.3.1 Data Formats in General Registers .....................................................................
2.3.2 Memory Data Formats........................................................................................
Addressing Modes ..........................................................................................................
2.4.1 Addressing Modes ..............................................................................................
2.4.2 Effective Address Calculation ............................................................................
Instruction Set.................................................................................................................
2.5.1 Data Transfer Instructions ..................................................................................
2.5.2 Arithmetic Operations ........................................................................................
2.5.3 Logic Operations ................................................................................................
2.5.4 Shift Operations ..................................................................................................
2.5.5 Bit Manipulations ...............................................................................................
2.5.6 Branching Instructions........................................................................................
2.5.7 System Control Instructions ...............................................................................
2.5.8 Block Data Transfer Instruction .........................................................................
Basic Operational Timing...............................................................................................
2.6.1 Access to On-Chip Memory (RAM, ROM) .......................................................
2.6.2 Access to On-Chip Peripheral Modules .............................................................
CPU States ......................................................................................................................
2.7.1 Overview.............................................................................................................
2.7.2 Program Execution State ...................................................................................
2.7.3 Program Halt State..............................................................................................
2.7.4 Exception-Handling State...................................................................................
2.8
2.9
Memory Map ..................................................................................................................
2.8.1 Memory Map ......................................................................................................
Application Notes ...........................................................................................................
2.9.1 Notes on Data Access .........................................................................................
2.9.2 Notes on Bit Manipulation..................................................................................
2.9.3 Notes on Use of the EEPMOV Instruction.........................................................
45
45
46
46
48
54
Section 3
3.1
3.2
Exception Handling
...................................................................................... 55
55
55
55
55
56
57
57
59
67
68
69
74
75
75
76
3.3
3.4
Overview.........................................................................................................................
Reset ............................................................................................................................
3.2.1 Overview.............................................................................................................
3.2.2 Reset Sequence ...................................................................................................
3.2.3 Interrupt Immediately after Reset.......................................................................
Interrupts.........................................................................................................................
3.3.1 Overview.............................................................................................................
3.3.2 Interrupt Control Registers .................................................................................
3.3.3 External Interrupts ..............................................................................................
3.3.4 Internal Interrupts ...............................................................................................
3.3.5 Interrupt Operations............................................................................................
3.3.6 Interrupt Response Time.....................................................................................
Application Notes ...........................................................................................................
3.4.1 Notes on Stack Area Use ....................................................................................
3.4.2 Notes on Rewriting Port Mode Registers ...........................................................
Section 4
4.1
Clock Pulse Generators
............................................................................... 79
79
79
79
80
83
86
87
4.2
4.3
4.4
4.5
Overview.........................................................................................................................
4.1.1 Block Diagram....................................................................................................
4.1.2 System Clock and Subclock ...............................................................................
System Clock Generator .................................................................................................
Subclock Generator ........................................................................................................
Prescalers ........................................................................................................................
Note on Oscillators .........................................................................................................
Section 5
5.1
5.2
Power-Down Modes
..................................................................................... 89
89
92
95
95
95
96
96
5.3
Overview.........................................................................................................................
5.1.1 System Control Registers ...................................................................................
Sleep Mode .....................................................................................................................
5.2.1 Transition to Sleep Mode....................................................................................
5.2.2 Clearing Sleep Mode ..........................................................................................
Standby Mode.................................................................................................................
5.3.1 Transition to Standby Mode ...............................................................................
5.4
5.5
5.6
5.7
5.8
5.3.2 Clearing Standby Mode ...................................................................................... 96
5.3.3 Oscillator Settling Time after Standby Mode is Cleared .................................... 97
Watch Mode.................................................................................................................... 98
5.4.1 Transition to Watch Mode .................................................................................. 98
5.4.2 Clearing Watch Mode ......................................................................................... 98
5.4.3 Oscillator Settling Time after Watch Mode is Cleared ....................................... 98
Subsleep Mode................................................................................................................ 99
5.5.1 Transition to Subsleep Mode .............................................................................. 99
5.5.2 Clearing Subsleep Mode..................................................................................... 99
Subactive Mode .............................................................................................................. 100
5.6.1 Transition to Subactive Mode............................................................................. 100
5.6.2 Clearing Subactive Mode ................................................................................... 100
5.6.3 Operating Frequency in Subactive Mode ........................................................... 100
Active (medium-speed) Mode ........................................................................................ 101
5.7.1 Transition to Active (medium-speed) Mode....................................................... 101
5.7.2 Clearing Active (medium-speed) Mode ............................................................. 101
5.7.3 Operating Frequency in Active (medium-speed) Mode ..................................... 101
Direct Transfer ................................................................................................................ 102
Section 6
6.1
6.2
ROM
................................................................................................................. 105
6.3
6.4
Overview......................................................................................................................... 105
6.1.1 Block Diagram ................................................................................................... 105
PROM Mode................................................................................................................... 106
6.2.1 Selection of PROM Mode ................................................................................. 106
6.2.2 Socket Adapter Pin Arrangement and Memory Map ......................................... 106
Programming .................................................................................................................. 109
6.3.1 Programming and Verification............................................................................ 110
6.3.2 Programming Precautions................................................................................... 114
Reliability of Programmed Data..................................................................................... 115
Section 7
7.1
RAM
................................................................................................................. 117
Overview......................................................................................................................... 117
7.1.1 Block Diagram ................................................................................................... 117
Section 8
I/O Ports
........................................................................................................... 119
8.1 Overview ............................................................................................................................ 119
8.2
Port 1 ............................................................................................................................ 121
8.2.1 Overview............................................................................................................. 121
8.2.2 Register Configuration and Description ............................................................. 121
8.2.3 Pin Functions ...................................................................................................... 125
8.2.4 Pin States ............................................................................................................ 126
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