CY28416
Next Generation FTG for Intel
®
Architecture
Features
• Supports Intel Pentium
®
4-Type CPUs
• Selectable CPU Frequencies
• Two Differential CPU Clock Pairs
• Four 100 MHz Differential SRC Clock Pairs
• One CPU/SRC Selectable Differential Clock Pair
• One 96 MHz Differential Dot Clock Support
• Two 48 MHz Clocks
• Four 33 MHz PCI Clocks
CPU
x2 / x3
SRC
x4 / x5
PCI
x6
DOT
x1
USB
x2
REF
x2
• Two 33 MHz PCI Free Running Clocks
• Low Voltage Frequency Select Input
• I
2
C Support Byte/Word/Block Read/Write Capabilities
• Ideal Lexmark Spread Spectrum Profile for Maximum
EMI Reduction
• 3.3V Power Supply
• 48-pin SSOP Package
Block Diagram
XIN
XOUT
Pin Configuration
VDD_REF
REF
XTAL
OSC
PLL1
PLL Ref Freq
Divider
Network
VDD_CPU
CPUT[0:1], CPUC[0:1],
CPU2/SRC4
VDD_SRC
SRCT[0:3], SRCC[0:3]
FS_[C:A]
VTT_PWRGD#
IREF
VDD_PCI
PCI[0:3]
VDD_PCIF
PCIF[0:1]
PD
VDD_48MHz
PLL2
DOT96T
DOT96C
48MHz0
48MHz1
SDATA
SCLK
I
2
C
Logic
SCLK
SDATA
XOUT
XIN
VSS_REF
REF1/FS_A
REF0/FS_C
VDD_REF
PCI0
PCI1
VDD_PCI
VSS_PCI
PCI2
PCI3
VSS_PCI
VDD_PCI
PCIF0/TESTSEL
PCIF1/ITPEN
VDD_48
48MHz0/FS_B
48MHz1
VSS_48
DOT96T
DOT96C
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
VSS_CPU
CPUT0
CPUC0
VDD_CPU
CPUT1
CPUC1
IREF
VSSA
VDDA
CPUT2_ITP/SRCT4
CPUC2_ITP/SRCC4
VDD_SRC
VSS_SRC
SRCT3
SRCC3
VDD_SRC
SRCC2_SATA
SRCT2_SATA
SRCC1
SRCT1
VSS_SRC
SRCC0
SRCT0
VTT_PWRGD#/PD
48-PIN SSOP
CY28416
Rev 1.0, November 22, 2006
2200 Laurelwood Road, Santa Clara, CA 95054
Tel:(408) 855-0555
Fax:(408) 855-0550
Page 1 of 14
www.SpectraLinear.com
CY28416
Pin Definition
Pin No.
47,46,44,43
39,38
Name
CPUT/C[0:1]
CPUT2_ITP/SRCT4
CPUC2_ITP/SRCC4
DOT96T, DOT96C
FS_A/REF1
FS_B/48 MHz0
FS_C/REF0
IREF
ITP_EN/PCIF1
PCI
48 MHz1
SCLK
SDATA
SRCT/C[0:3]
SRCT2_SATA,
SRCC2_SATA
TEST_SEL/PCIF0
VDD_48
VDD_CPU
VDD_PCI
VDD_REF
VDD_SRC
VDDA
VSS_48
VSS_CPU
VSS_PCI
VSS_REF
VSS_SRC
VSSA
VTT_PWRGD#/PD
Type
O, DIF
Differential CPU clock output.
O, DIF Selectable Differential CPU or SRC clock output.
ITP_EN = 0 @VTT_PWRGD# assertion PIN 39,38 = SRCT4,SRCC4
ITP_EN = 1 @VTT_PWRGD# assertion PIN 39,38 = CPUT2_ITP,CPUC2_ITP
O, DIF
Differential 96 MHz clock output.
I/O, SE
3.3V tolerant input for CPU frequency/REF clock
Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications
.
I/O, SE
3.3V tolerant input for CPU frequency/48 MHz clock
Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications
.
I
/
O, SE
3.3V tolerant input for CPU frequency/REF clock
Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications
.
I
A precision resistor is attached to this pin, which is connected to the internal
current reference.
Description
23,24
6
20
7
42
18
9,10,13,14
21
1
2
26,27,29,30,
34,35
31,32
17
19
45
11, 16
8
33, 37
40
22
48
12, 15
5
28, 36
41
25
I/O, SE
Enable SRC4 or CPU2_ITP/PCIF clock.
(sampled on the VTT_PWRGD# assertion). 0 = SRC4, 1 = CPU2_ITP
O, SE
33 MHz clock output.
O, SE
48 MHz clock output.
(Uses same control SMBus register as 48 MHz0 to control
enable/disable.)
I
I/O
SMBus compatible SCLOCK.
SMBus compatible SDATA.
O, DIF
Differential Serial reference clock.
O, DIF
Differential Serial reference clock.
Recommended output for SATA
I/O, SE,
LVTTL input for selecting HI-Z or Normal operation/33 MHz Clock
PD 0 = Normal operation, 1 = HI-Z when VTT_PWRGD# is sampled
PWR
PWR
PWR
PWR
PWR
PWR
GND
GND
GND
GND
GND
GND
I, PD
3.3V power supply for outputs
3.3V power supply for outputs
3.3V power supply for outputs
3.3V power supply for outputs
3.3V power supply for outputs
3.3V power supply for PLL
Ground for outputs
Ground for outputs
Ground for outputs
Ground for outputs
Ground for outputs
Ground for PLL
3.3V LVTTL Input.
This pin is a level-sensitive strobe used to latch the FS_A,
FS_B, FS_C/TEST_SEL, and PCIF0/ITP_EN Inputs. After asserting
VTT_PWRGD# (active LOW), this pin becomes a realtime input for asserting
power-down (active HIGH)
14.318 MHz Crystal Input
14.318 MHz Crystal Output
4
3
XIN
XOUT
I
O
Rev 1.0, November 22, 2006
Page 2 of 14
CY28416
Frequency Select Pins (FS_A, FS_B, and FS_C)
Host clock frequency selection is achieved by applying the
appropriate logic levels to FS_A, FS_B, FS_C inputs prior to
VTT_PWRGD# assertion (as seen by the clock synthesizer).
Upon VTT_PWRGD# being sampled LOW by the clock chip
(indicating processor VTT voltage is stable), the clock chip
samples the FS_A, FS_B, and FS_C input values. For all logic
levels of FS_A, FS_B, and FS_C VTT_PWRGD# employs a
one-shot functionality in that once a valid LOW on
VTT_PWRGD# has been sampled, all further VTT_PWRGD#,
FS_A, FS_B, and FS_C transitions will be ignored, except in
test mode.
initialize to their default setting upon power-up, and therefore
use of this interface is optional. Clock device register changes
are normally made upon system initialization, if any are
required. The interface cannot be used during system
operation for power management functions.
Data Protocol
The clock driver serial protocol accepts byte write, byte read,
block write, and block read operations from the controller. For
block write/read operation, the bytes must be accessed in
sequential order from lowest to highest byte (most significant
bit first) with the ability to stop after any complete byte has
been transferred. For byte write and byte read operations, the
system controller can access individually indexed bytes. The
offset of the indexed byte is encoded in the command code,
as described in
Table 2.
The block write and block read protocol is outlined in
Table 3
while
Table 4
outlines the corresponding byte write and byte
read protocol. The slave receiver address is 11010010 (D2h).
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer,
a two-signal serial interface is provided. Through the Serial
Data Interface, various device functions, such as individual
clock output buffers, can be individually enabled or disabled.
The registers associated with the Serial Data Interface
Table 1. Frequency Select Table (FS_A FS_B)
FS_C
1
0
0
0
0
1
1
1
T
FS_B
0
0
1
1
0
0
1
1
FS_A
1
1
1
0
0
0
0
1
CPU
100 MHz
133 MHz
166 MHz
200 MHz
266 MHz
SRC
100 MHz
100 MHz
100 MHz
100 MHz
100 MHz
PCIF/PCI
33 MHz
33 MHz
33 MHz
33 MHz
33 MHz
REF0
14.318 MHz
14.318 MHz
14.318 MHz
14.318 MHz
14.318 MHz
DOT96
96 MHz
96 MHz
96 MHz
96 MHz
96 MHz
USB
48 MHz
48 MHz
48 MHz
48 MHz
48 MHz
RESERVED
Table 2. Command Code Definition
Bit
7
(6:0)
Description
0 = Block read or block write operation, 1 = Byte read or byte write operation
Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be '0000000'
Table 3. Block Read and Block Write Protocol
Block Write Protocol
Bit
1
8:2
9
10
18:11
19
27:20
28
36:29
37
45:38
Start
Slave address – 7 bits
Write
Acknowledge from slave
Command Code – 8 Bits
Acknowledge from slave
Byte Count – 8 bits
(Skip this step if I
2
C_EN bit set)
Acknowledge from slave
Data byte 1 – 8 bits
Acknowledge from slave
Data byte 2 – 8 bits
Description
Bit
1
8:2
9
10
18:11
19
20
27:21
28
29
37:30
Start
Slave address – 7 bits
Write
Acknowledge from slave
Command Code – 8 Bits
Acknowledge from slave
Repeat start
Slave address – 7 bits
Read = 1
Acknowledge from slave
Byte Count from slave – 8 bits
Block Read Protocol
Description
Rev 1.0, November 22, 2006
Page 3 of 14
CY28416
Table 3. Block Read and Block Write Protocol
(continued)
Block Write Protocol
Bit
46
....
....
....
....
Description
Acknowledge from slave
Data Byte /Slave Acknowledges
Data Byte N –8 bits
Acknowledge from slave
Stop
Bit
38
46:39
47
55:48
56
....
....
....
...
Acknowledge
Data byte 1 from slave – 8 bits
Acknowledge
Data byte 2 from slave – 8 bits
Acknowledge
Data bytes from slave / Acknowledge
Data Byte N from slave – 8 bits
NOT Acknowledge
Stop
Block Read Protocol
Description
Table 4. Byte Read and Byte Write Protocol
Byte Write Protocol
Bit
1
8:2
9
10
18:11
19
27:20
28
29
Start
Slave address – 7 bits
Write
Acknowledge from slave
Command Code – 8 bits
Acknowledge from slave
Data byte – 8 bits
Acknowledge from slave
Stop
Description
Bit
1
8:2
9
10
18:11
19
20
27:21
28
29
37:30
38
39
Start
Slave address – 7 bits
Write
Acknowledge from slave
Command Code – 8 bits
Acknowledge from slave
Repeated start
Slave address – 7 bits
Read
Acknowledge from slave
Data from slave – 8 bits
NOT Acknowledge
Stop
Byte Read Protocol
Description
Control Registers
Byte 0: Control Register 0
Bit
7
6
5
4
3
2
1
0
@Pup
1
1
1
1
1
1
1
1
Name
CPUT2_ITP/SRCT4
CPUC2_ITP/SRCC4
RESERVED
RESERVED
SRC[T/C]3
SRC[T/C]2_SATA
SRC[T/C]1
SRC[T/C]0
RESERVED
Description
CPU[T/C]2_ITP/SRC[T/C]4 Output Enable
0 = Disable (Hi-Z), 1 = Enable
RESERVED, Set = 1
RESERVED, Set = 1
SRC[T/C]3 Output Enable
0 = Disable (Hi-Z), 1 = Enable
SRC[T/C]2_SATA Output Enable
0 = Disable (Hi-Z), 1 = Enable
SRC[T/C]1 Output Enable
0 = Disable (Hi-Z), 1 = Enable
SRC[T/C]0 Output Enable
0 = Disable (Hi-Z), 1 = Enable
RESERVED, Set = 1
Rev 1.0, November 22, 2006
Page 4 of 14
CY28416
Byte 1: Control Register 1
Bit
7
6
5
4
3
2
1
0
@Pup
1
1
1
1
1
1
1
0
Name
Spread Selection
DOT_96T/C
48 MHz0, 48 MHz1
REF0
REF1
CPU[T/C]1
CPU[T/C]0
CPUT/C
SRCT/C
PCIF
PCI
Description
0=Center Spread, 1= Down Spread (Default)
DOT_96 MHz Output Enable
0 = Disable (Hi-Z), 1 = Enabled
48-MHz Output Enable
0 = Disabled, 1 = Enabled
REF Output Enable
0 = Disabled, 1 = Enabled
REF Output Enable
0 = Disabled, 1 = Enabled
CPU[T/C]1 Output Enable
0 = Disable (Hi-Z), 1 = Enabled
CPU[T/C]0 Output Enable
0 = Disable (Hi-Z), 1 = Enabled
Spread Spectrum Enable
0 = Spread off, 1 = Spread on
Byte 2: Control Register 2
Bit
7
6
5
4
3
2
1
0
@Pup
1
1
1
1
1
1
1
1
Name
PCI3
PCI2
RESERVED
RESERVED
PCI1
PCI0
PCIF1
PCIF0
PCI3 Output Enable
0 = Disabled, 1 = Enabled
PCI2 Output Enable
0 = Disabled, 1 = Enabled
RESERVED, Set = 1
RESERVED, Set = 1
PCI1 Output Enable
0 = Disabled, 1 = Enabled
PCI0 Output Enable
0 = Disabled, 1 = Enabled
PCIF2 Output Enable
0 = Disabled, 1 = Enabled
PCIF1 Output Enable
0 = Disabled, 1 = Enabled
Description
Byte 3: Control Register 3
Bit
7
6
5
4
3
2
1
0
@Pup
0
0
0
0
0
0
0
0
Name
SRC[T/C]4
RESERVED
RESERVED
SRC[T/C]3
SRC2_SATA
SRC[T/C]1
SRC[T/C]0
RESERVED
Description
Allow control of SRC[T/C]4 with assertion of SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
RESERVED, Set = 0
RESERVED, Set = 0
Allow control of SRC[T/C]3 with assertion of SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
Allow control of SRC2_SATA with assertion of SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
Allow control of SRC[T/C]1 with assertion of SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
Allow control of SRC[T/C]1 with assertion of SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
RESERVED, Set = 0
Rev 1.0, November 22, 2006
Page 5 of 14
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