128Kx8 High Speed Static RAM(3.3V Operating), Revolutionary Pin out.
Operated at Commercial and Industrial Temperature Range.
CMOS SRAM
Revision History
Rev. No.
Rev. 0.0
Rev. 1.0
History
Initial release with Design Target.
Release to Preliminary Data Sheet.
1.1. Replace Design Target to Preliminary
Release to final Data Sheet.
2.1. Delete Preliminary
Add Low Power Product and update D.C parameters.
3.1. Add Low Power Products with Isb1=0.5mA and Data Retention
Mode(L-ver. only)
3.2. Update D.C parameters.
Previous spec.
Updated spec.
Items
(12/15/17/20ns part)
(12/15/17/20ns part)
Icc
170/165/160/155mA
140/135/135/130mA
Isb
30mA
20mA
Isb1
10mA
5mA
Add Industrial Temperature Range parts and 300mil 32-SOJ PKG
4.1. Add 32-Pin 300mil-SOJ Package.
4.2. Add Industrial Temperature Range parts with the same parame-
ters as Commercial Temperature Range parts.
4.2.1. Add KM68V1002AI/ALI parts for Industrial Temperature
Range.
4.2.2. Add ordering information.
4.2.3. Add the condition for operating at Industrial Temp. Range.
4.3. Add timing diagram to define t
WP
as
″(Timing
Wave Form of
Write Cycle(CS=Controlled)″
5.1. Delete L-version.
5.2. Delete Data Retention Characteristics and Wavetorm.
5.3. Delete 17ns Part
5.4. Add Capacitive load of the test environment in A.C test load
Draft Data
Jan. 18th, 1995
Apr. 22th, 1995
Remark
Design Target
Preliminary
Rev. 2.0
Feb. 29th, 1996
Final
Rev. 3.0
Jul. 16th, 1996
Final
Rev. 4.0
Jun. 2nd, 1997
Final
Rev. 5.0
Feb. 25th, 1998
Final
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right
to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this
device. If you have any questions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
-1-
Rev 5.0
February 1998
PRELIMINARY
KM68V1002A, KM68V1002AI
128K x 8 Bit High-Speed CMOS Static RAM(3.3V Operating)
FEATURES
• Fast Access Time 12, 15, 20ns(Max.)
• Low Power Dissipation
Standby (TTL)
: 20mA(Max.)
(CMOS) : 5mA(Max.)
Operating KM68V1002A - 12 : 140mA(Max.)
KM68V1002A - 15 : 135mA(Max.)
KM68V1002A - 20 : 130mA(Max.)
• Single 3.3
±
0.3V Power Supply
• TTL Compatible Inputs and Outputs
• Fully Static Operation
- No Clock or Refresh required
• Three State Outputs
• Center Power/Ground Pin Configuration
• Standard Pin Configuration
KM68V1002AJ : 32-SOJ-400
KM68V1002AT : 32-TSOP2-400F
CMOS SRAM
GENERAL DESCRIPTION
The KM68V1002A is a 1,048,576-bit high-speed Static Ran-
dom Access Memory organized as 131,072 words by 8 bits.
The KM68V1002A uses 8 common input and output lines and
has an output enable pin which operates faster than address
access time at read cycle. The device is fabricated using Sam-
sung′s advanced CMOS process and designed for high-speed
circuit technology. It is particularly well suited for use in high-
density high-speed system applications. The KM68V1002A is
packaged in a 400mil 32-pin plastic SOJ or TSOP2 forward.
ORDERING INFORMATION
KM68V1002A -12/15/20
KM68V1002AI -12/15/20
Commercial Temp.
Industrial Temp.
PIN CONFIGURATION
(Top View)
A
0
1
2
3
4
5
6
7
8
9
32 A
16
31 A
15
30 A
14
29 A
13
28
OE
FUNCTIONAL BLOCK DIAGRAM
Clk Gen.
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
1
A
2
Pre-Charge Circuit
A
3
CS
I/O
1
I/O
2
27 I/O
8
26 I/O
7
Row Select
Memory Array
512 Rows
256x8 Columns
Vcc
Vss
SOJ/
TSOP2
25 Vss
24 Vcc
23 I/O
6
22 I/O
5
21 A
12
20 A
11
19 A
10
18
17
A
9
A
8
I/O
3
10
I/O
4
11
WE
A
4
12
13
14
15
16
I/O
1
~ I/O
8
Data
Cont.
CLK
Gen.
I/O Circuit
Column Select
A
5
A
6
A
7
A
9
A
10
A
11
A
12
A
13
A
14
A
15
A
16
PIN FUNCTION
Pin Name
Pin Function
Address Inputs
Write Enable
Chip Select
Output Enable
Data Inputs/Outputs
Power(+3.3V)
Ground
A
0
- A
16
WE
CS
OE
I/O
1
~ I/O
8
V
CC
V
SS
CS
WE
OE
-2-
Rev 5.0
February 1998
PRELIMINARY
KM68V1002A, KM68V1002AI
ABSOLUTE MAXIMUM RATINGS*
Parameter
Voltage on Any Pin Relative to V
SS
Voltage on V
CC
Supply Relative to V
SS
Power Dissipation
Storage Temperature
Operating Temperature
Commercial
Industrial
Symbol
V
IN
, V
OUT
V
CC
P
D
T
STG
T
A
T
A
Rating
-0.5 to 4.6
-0.5 to 4.6
1.0
-65 to 150
0 to 70
-40 to 85
Unit
V
V
CMOS SRAM
W
°C
°C
°C
*
Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS
(T
A
=0 to 70°C)
Parameter
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
Symbol
V
CC
V
SS
V
IH
V
IL
Min
3.0
0
2.2
-0.3*
Typ
3.3
0
-
-
Max
3.6
0
V
CC
+ 0.3**
0.8
Unit
V
V
V
V
NOTE: The above parameters are also guaranteed at industrial temperature range.
*
V
IL
(Min) = -2.0V a.c(Pulse Width≤10ns) for I≤20mA
**
V
IH
(Max) = V
CC +
2.0V a.c (Pulse Width≤10ns) for I≤20mA
DC AND OPERATING CHARACTERISTICS
(T
A
=0 to 70°C, Vcc=3.3±0.3V, unless otherwise specified)
Parameter
Input Leakage Current
Output Leakage Current
Operating Current
Symbol
I
LI
I
LO
I
CC
Test Conditions
V
IN
= V
SS
to V
CC
CS=V
IH
or OE=V
IH
or WE=V
IL
V
OUT
=V
SS
to V
CC
Min. Cycle, 100% Duty
CS=V
IL,
V
IN
=V
IH
or V
IL,
I
OUT
=0mA
Min. Cycle, CS=V
IH
f=0MHz, CS
≥V
CC
-0.2V,
V
IN
≥V
CC
-0.2V or V
IN
≤0.2V
I
OL
=8mA
I
OH
=-4mA
12ns
15ns
20ns
Standby Current
I
SB
I
SB1
Output Low Voltage Level
Output High Voltage Level
V
OL
V
OH
Min
-2
-2
-
-
-
-
-
-
2.4
Max
2
2
140
135
130
20
5
0.4
-
mA
mA
V
V
Unit
µA
µA
mA
NOTE: The above parameters are also guaranteed at industrial temperature range.
CAPACITANCE*
(T
A
=25°C, f=1.0MHz)
Item
Input/Output Capacitance
Input Capacitance
* NOTE : Capacitance is sampled and not 100% tested.
Symbol
C
I/O
C
IN
Test Conditions
V
I/O
=0V
V
IN
=0V
MIN
-
-
Max
8
6
Unit
pF
pF
-3-
Rev 5.0
February 1998
PRELIMINARY
KM68V1002A, KM68V1002AI
AC CHARACTERISTICS
(T
A
=0 to 70°C, V
CC
=3.3±0.3V, unless otherwise noted.)
TEST CONDITIONS
Parameter
Input Pulse Levels
Input Rise and Fall Times
Input and Output timing Reference Levels
Output Loads
NOTE: The above test conditions are also applied at industrial temperature range.
CMOS SRAM
Value
0V to 3V
3ns
1.5V
See below
Output Loads(A)
Output Loads(B)
for t
HZ
, t
LZ
, t
WHZ
, t
OW
, t
OLZ
& t
OHZ
+3.3V
R
L
= 50Ω
D
OUT
V
L
= 1.5V
Z
O
= 50Ω
30pF*
319Ω
D
OUT
353Ω
5pF*
* Capacitive Load consists of all components of the
test environment.
* Including Scope and Jig Capacitance
READ CYCLE
Parameter
Read Cycle Time
Address Access Time
Chip Select to Output
Output Enable to Valid Output
Chip Enable to Low-Z Output
Output Enable to Low-Z Output
Chip Disable to High-Z Output
Output Disable to High-Z Output
Output Hold from Address Change
Chip Selection to Power Up Time
Chip Selection to Power DownTime
Symbol
t
RC
t
AA
t
CO
t
OE
t
LZ
t
OLZ
t
HZ
t
OHZ
t
OH
t
PU
t
PD
KM68V1002A-12
Min
12
-
-
-
3
0
0
0
3
0
-
Max
-
12
12
6
-
-
6
6
-
-
12
KM68V1002A-15
Min
15
-
-
-
3
0
0
0
3
0
-
Max
-
15
15
7
-
-
7
7
-
-
15
KM68V1002A-20
Min
20
-
-
-
3
0
0
0
3
0
-
Max
-
20
20
9
-
-
9
9
-
-
20
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTE: The above parameters are also guaranteed at industrial temperature range.
-4-
Rev 5.0
February 1998
PRELIMINARY
KM68V1002A, KM68V1002AI
WRITE CYCLE
Parameter
Write Cycle Time
Chip Select to End of Write
Address Set-up Time
Address Valid to End of Write
Write Pulse Width(OE High)
Write Pulse Width(OE Low)
Write Recovery Time
Write to Output High-Z
Data to Write Time Overlap
Data Hold from Write Time
End Write to Output Low-Z
Symbol
t
WC
t
CW
t
AS
t
AW
t
WP
t
WP1
t
WR
t
WHZ
t
DW
t
DH
t
OW
KM6161002A-12
Min
12
8
0
8
8
12
0
0
6
0
3
Max
-
-
-
-
-
-
-
6
-
-
-
KM6161002A-15
Min
15
10
0
10
10
15
0
0
7
0
3
Max
-
-
-
-
-
-
-
7
-
-
-
KM6161002A-20
Min
20
12
0
12
12
20
0
0
9
0
3
Max
-
-
-
-
-
-
-
9
-
-
-
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CMOS SRAM
NOTE: The above parameters are also guaranteed at industrial temperature range.
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