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HYB25D256160BTL-5A: 产品描述256MBit Double Data Rata SDRAM; 产品类别存储存储; 文件大小300KB，共29页; 制造商Infineon(英飞凌); 官网地址http://www.infineon.com/

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HYB25D256160BTL-5A概述

256MBit Double Data Rata SDRAM

HYB25D256160BTL-5A规格参数

参数名称	属性值
是否Rohs认证	不符合
厂商名称	Infineon(英飞凌)
零件包装代码	TSOP2
包装说明	TSOP2, TSSOP66,.46
针数	66
Reach Compliance Code	compli
ECCN代码	EAR99
访问模式	FOUR BANK PAGE BURST
最长访问时间	0.5 ns
其他特性	AUTO/SELF REFRESH
最大时钟频率 (fCLK)	200 MHz
I/O 类型	COMMON
交错的突发长度	2,4,8
JESD-30 代码	R-PDSO-G66
JESD-609代码	e0
长度	22.22 mm
内存密度	268435456 bi
内存集成电路类型	DDR DRAM
内存宽度	16
功能数量	1
端口数量	1
端子数量	66
字数	16777216 words
字数代码	16000000
工作模式	SYNCHRONOUS
最高工作温度	70 °C
最低工作温度
组织	16MX16
输出特性	3-STATE
封装主体材料	PLASTIC/EPOXY
封装代码	TSOP2
封装等效代码	TSSOP66,.46
封装形状	RECTANGULAR
封装形式	SMALL OUTLINE, THIN PROFILE
峰值回流温度（摄氏度）	NOT SPECIFIED
电源	2.5 V
认证状态	Not Qualified
刷新周期	8192
座面最大高度	1.2 mm
自我刷新	YES
连续突发长度	2,4,8
最大待机电流	0.009 A
最大压摆率	0.31 mA
最大供电电压 (Vsup)	2.7 V
最小供电电压 (Vsup)	2.5 V
标称供电电压 (Vsup)	2.6 V
表面贴装	YES
技术	CMOS
温度等级	COMMERCIAL
端子面层	Tin/Lead (Sn/Pb)
端子形式	GULL WING
端子节距	0.65 mm
端子位置	DUAL
处于峰值回流温度下的最长时间	NOT SPECIFIED
宽度	10.16 mm

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HYB25D256[800/160]BT(L)

-[5/5A]

256MBit Double Data Rata SDRAM

Preliminary

DDR400 Data Sheet Addendum Jan. 2003, V0.9

Features

CAS Latency and Clock Frequency

CAS Latency

2.5

Maximum Operating Frequency (MHz)

DDR400B

DDR400A

-5

-5A

133

166

200

• Double data rate architecture: two data transfers

per clock cycle

• Bidirectional data strobe (DQS) is transmitted

and received with data, to be used in capturing

data at the receiver

• DQS is edge-aligned with data for reads and is

center-aligned with data for writes

• Differential clock inputs (CK and CK)

• Four internal banks for concurrent operation

• Data mask (DM) for write data

• DLL aligns DQ and DQS transitions with CK

transitions

• Commands entered on each positive CK edge;

data and data mask referenced to both edges of

DQS

• Burst Lengths: 2, 4, or 8

• CAS Latency: (1.5), 2, 2.5, (3)

• Auto Precharge option for each burst access

• Auto Refresh and Self Refresh Modes

• 7.8ms Maximum Average Periodic Refresh

Interval (8k refresh)

• 2.5V (SSTL_2 compatible) I/O

• V

DDQ

= 2.6V ± 0.1V / V

= 2.6V ± 0.1V

• TSOP66 package

Description

The 256Mb DDR SDRAM is a high-speed CMOS,

dynamic random-access memory containing 268,435,456

bits. It is internally configured as a quad-bank DRAM.

The 256Mb DDR SDRAM uses a double-data-rate archi-

tecture to achieve high-speed operation. The double data

rate architecture is essentially a

prefetch architecture

with an interface designed to transfer two data words per

clock cycle at the I/O pins. A single read or write access

for the 256Mb DDR SDRAM effectively consists of a sin-

gle

2n-bit

wide, one clock cycle data transfer at the inter-

nal DRAM core and two corresponding n-bit wide, one-

half-clock-cycle data transfers at the I/O pins.

A bidirectional data strobe (DQS) is transmitted externally,

along with data, for use in data capture at the receiver.

DQS is a strobe transmitted by the DDR SDRAM during

Reads and by the memory controller during Writes. DQS

is edge-aligned with data for Reads and center-aligned

with data for Writes.

The 256Mb DDR SDRAM operates from a differential

clock (CK and CK; the crossing of CK going HIGH and CK

going LOW is referred to as the positive edge of CK).

Commands (address and control signals) are registered at

every positive edge of CK. Input data is registered on both

edges of DQS, and output data is referenced to both

edges of DQS, as well as to both edges of CK.

Read and write accesses to the DDR SDRAM are burst

oriented; accesses start at a selected location and con-

tinue for a programmed number of locations in a pro-

grammed sequence. Accesses begin with the registration

of an Active command, which is then followed by a Read

or Write command. The address bits registered coincident

with the Active command are used to select the bank and

row to be accessed. The address bits registered coinci-

2003-01-10, V0.9

dent with the Read or Write command are used to select

the bank and the starting column location for the burst

access.

The DDR SDRAM provides for programmable Read or

Write burst lengths of 2, 4 or 8 locations. An Auto Pre-

charge function may be enabled to provide a self-timed

row precharge that is initiated at the end of the burst

access.

As with standard SDRAMs, the pipelined, multibank archi-

tecture of DDR SDRAMs allows for concurrent operation,

thereby providing high effective bandwidth by hiding row

precharge and activation time.

An auto refresh mode is provided along with a power-sav-

ing power-down mode. All inputs are compatible with the

JEDEC Standard for SSTL_2. All outputs are SSTL_2,

Class II compatible.

Note:

The functionality described and the timing specifi-

cations included in this data sheet are for the DLL Enabled

mode of operation.

Page 1 of 29

HYB25D256160BTL-5A相似产品对比

	HYB25D256160BTL-5A	HYB25D256160BT-5	HYB25D256160BT-5A	HYB25D256160BTL-5	HYB25D256800BT	HYB25D256800BT-5A	HYB25D256800BT-5	HYB25D256800BTL-5	HYB25D256800BTL-5A
描述	256MBit Double Data Rata SDRAM	256MBit Double Data Rata SDRAM	256MBit Double Data Rata SDRAM	256MBit Double Data Rata SDRAM	256MBit Double Data Rata SDRAM	256MBit Double Data Rata SDRAM	256MBit Double Data Rata SDRAM	256MBit Double Data Rata SDRAM	256MBit Double Data Rata SDRAM
是否Rohs认证	不符合	不符合	不符合	不符合	-	不符合	不符合	不符合	不符合
零件包装代码	TSOP2	TSOP2	TSOP2	TSOP2	-	TSOP2	TSOP2	TSOP2	TSOP2
包装说明	TSOP2, TSSOP66,.46	TSOP2, TSSOP66,.46	TSOP2, TSSOP66,.46	TSOP2, TSSOP66,.46	-	TSOP2, TSSOP66,.46	TSOP2, TSSOP66,.46	TSOP2, TSSOP66,.46	TSOP2, TSSOP66,.46
针数	66	66	66	66	-	66	66	66	66
Reach Compliance Code	compli	compli	compli	compli	-	compliant	compli	compli	compli
ECCN代码	EAR99	EAR99	EAR99	EAR99	-	EAR99	EAR99	EAR99	EAR99
访问模式	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST	-	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST
最长访问时间	0.5 ns	0.5 ns	0.5 ns	0.5 ns	-	0.5 ns	0.5 ns	0.5 ns	0.5 ns
其他特性	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	-	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH
最大时钟频率 (fCLK)	200 MHz	200 MHz	200 MHz	200 MHz	-	200 MHz	200 MHz	200 MHz	200 MHz
I/O 类型	COMMON	COMMON	COMMON	COMMON	-	COMMON	COMMON	COMMON	COMMON
交错的突发长度	2,4,8	2,4,8	2,4,8	2,4,8	-	2,4,8	2,4,8	2,4,8	2,4,8
JESD-30 代码	R-PDSO-G66	R-PDSO-G66	R-PDSO-G66	R-PDSO-G66	-	R-PDSO-G66	R-PDSO-G66	R-PDSO-G66	R-PDSO-G66
JESD-609代码	e0	-	e0	e0	-	e0	-	e0	e0
长度	22.22 mm	22.22 mm	22.22 mm	22.22 mm	-	22.22 mm	22.22 mm	22.22 mm	22.22 mm
内存密度	268435456 bi	268435456 bi	268435456 bi	268435456 bi	-	268435456 bit	268435456 bi	268435456 bi	268435456 bi
内存集成电路类型	DDR DRAM	DDR DRAM	DDR DRAM	DDR DRAM	-	DDR DRAM	DDR DRAM	DDR DRAM	DDR DRAM
内存宽度	16	16	16	16	-	8	8	8	8
功能数量	1	1	1	1	-	1	1	1	1
端口数量	1	1	1	1	-	1	1	1	1
端子数量	66	66	66	66	-	66	66	66	66
字数	16777216 words	16777216 words	16777216 words	16777216 words	-	33554432 words	33554432 words	33554432 words	33554432 words
字数代码	16000000	16000000	16000000	16000000	-	32000000	32000000	32000000	32000000
工作模式	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	-	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
最高工作温度	70 °C	70 °C	70 °C	70 °C	-	70 °C	70 °C	70 °C	70 °C
组织	16MX16	16MX16	16MX16	16MX16	-	32MX8	32MX8	32MX8	32MX8
输出特性	3-STATE	3-STATE	3-STATE	3-STATE	-	3-STATE	3-STATE	3-STATE	3-STATE
封装主体材料	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	-	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
封装代码	TSOP2	TSOP2	TSOP2	TSOP2	-	TSOP2	TSOP2	TSOP2	TSOP2
封装等效代码	TSSOP66,.46	TSSOP66,.46	TSSOP66,.46	TSSOP66,.46	-	TSSOP66,.46	TSSOP66,.46	TSSOP66,.46	TSSOP66,.46
封装形状	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	-	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
封装形式	SMALL OUTLINE, THIN PROFILE	SMALL OUTLINE, THIN PROFILE	SMALL OUTLINE, THIN PROFILE	SMALL OUTLINE, THIN PROFILE	-	SMALL OUTLINE, THIN PROFILE	SMALL OUTLINE, THIN PROFILE	SMALL OUTLINE, THIN PROFILE	SMALL OUTLINE, THIN PROFILE
峰值回流温度（摄氏度）	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	-	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
电源	2.5 V	2.5 V	2.5 V	2.5 V	-	2.5 V	2.5 V	2.5 V	2.5 V
认证状态	Not Qualified	Not Qualified	Not Qualified	Not Qualified	-	Not Qualified	Not Qualified	Not Qualified	Not Qualified
刷新周期	8192	8192	8192	8192	-	8192	8192	8192	8192
座面最大高度	1.2 mm	1.2 mm	1.2 mm	1.2 mm	-	1.2 mm	1.2 mm	1.2 mm	1.2 mm
自我刷新	YES	YES	YES	YES	-	YES	YES	YES	YES
连续突发长度	2,4,8	2,4,8	2,4,8	2,4,8	-	2,4,8	2,4,8	2,4,8	2,4,8
最大待机电流	0.009 A	0.009 A	0.009 A	0.009 A	-	0.009 A	0.009 A	0.009 A	0.009 A
最大压摆率	0.31 mA	0.31 mA	0.31 mA	0.31 mA	-	0.28 mA	0.28 mA	0.28 mA	0.28 mA
最大供电电压 (Vsup)	2.7 V	2.7 V	2.7 V	2.7 V	-	2.7 V	2.7 V	2.7 V	2.7 V
最小供电电压 (Vsup)	2.5 V	2.6 V	2.5 V	2.6 V	-	2.5 V	2.5 V	2.5 V	2.5 V
标称供电电压 (Vsup)	2.6 V	2.6 V	2.6 V	2.6 V	-	2.6 V	2.6 V	2.6 V	2.6 V
表面贴装	YES	YES	YES	YES	-	YES	YES	YES	YES
技术	CMOS	CMOS	CMOS	CMOS	-	CMOS	CMOS	CMOS	CMOS
温度等级	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	-	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL
端子面层	Tin/Lead (Sn/Pb)	-	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	-	Tin/Lead (Sn/Pb)	-	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)
端子形式	GULL WING	GULL WING	GULL WING	GULL WING	-	GULL WING	GULL WING	GULL WING	GULL WING
端子节距	0.65 mm	0.65 mm	0.65 mm	0.65 mm	-	0.65 mm	0.65 mm	0.65 mm	0.65 mm
端子位置	DUAL	DUAL	DUAL	DUAL	-	DUAL	DUAL	DUAL	DUAL
处于峰值回流温度下的最长时间	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	-	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
宽度	10.16 mm	10.16 mm	10.16 mm	10.16 mm	-	10.16 mm	10.16 mm	10.16 mm	10.16 mm
Base Number Matches	-	-	1	-	-	1	1	1	1

HYB25D256160BTL-5A

HYB25D256160BTL-5A概述

HYB25D256160BTL-5A规格参数

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HYB25D256160BTL-5A相似产品对比

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