HD66120T
(240-Channel Segment Driver for Dot-Matrix Graphic
Liquid Crystal Display)
Description
The HD66120T is a segment driver for dot-matrix
graphic liquid crystal display (LCD). It features a
maximum driving voltage of 40 V, enabling a high
duty cycle. This driver operates at about 3 V,
making it suitable for battery-driven applications
that make use of the low power dissipation of
liquid crystal elements. The HD66120T, packaged
in a fine-pitch slim tape carrier package (TCP),
helps to reduce the size of the frame around an
LCD panel.
Features
•
•
•
•
•
•
Duty cycle: 1/100 to 1/480
High LCD driving voltage: 14 to 40 V
240 LCD drive circuits
Low operating voltage: 2.7 to 5.5 V
4- and 8-bit data bus interface
High-speed shift clocks
— 10 MHz (max) at 3-V operation
— 20 MHz (max) at 5-V operation
•
•
•
•
Display off function
Slim-TCP package
Fine output lead pitch: 70
µm
Compact user area: 9.44 mm (when output lead
pitch is 70
µm)
• Internal chip enable signal generator
• Standby function
Pin Arrangement
240
239
238
237
236
Y240
Y239
Y238
Y237
Y236
Top view
Note: This figure does not specify the TCP dimensions; other TCP shapes are also possible.
VLCD1
V1L
V3L
V4L
V2L
GND1
V
CC
BS
EIO2
D0
D1
D2
D3
D4
D5
D6
D7
CL2
DISP
CL1
EIO1
M
SHL
GND2
V2R
V4R
V3R
V1R
VLCD2
5
4
3
2
1
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
560
261
262
263
264
265
266
267
268
269
Y5
Y4
Y3
Y2
Y1
HD66120T
1157
HD66120T
Block Diagram
Y1—Y240
V1L—V4L
M
V
LCD1
V
CC
GND1
CL1
LCD drive circuit
V1R—V4R
Level shifter
V
LCD2
GND2
Latch circuit 2
DISP
BS
Latch circuit 1
Latch circuit 1
D
0
—D
7
Data shifter
SHL
CL2
EIO2
Shift register
EIO1
1158
HD66120T
Block Functions
LCD Drive Circuit
The 240-bit LCD drive circuit generates four
voltage levels V1, V2, V3, and V4, for driving an
LCD panel. One of the four levels is output to the
corresponding Y pin, depending on the com-
bination of the M signal and the data in latch
circuit 2.
Level Shifter
The level shifter changes 5-V signals into high-
voltage signals for the LCD drive circuit.
Latch Circuit 2
240-bit latch circuit 2 latches data input from latch
circuit 1, and outputs the latched data to the level
shifter, both at the falling edge of each clock 1
(CL1) pulse.
Latch Circuit 1
240-bit latch circuit 1 latches 4-bit or 8-bit parallel
data input via the D
0
to D
7
pins at the timing
generated by the shift register.
Shift Register
The 60-bit shift register generates and outputs data
latch signals for latch circuit 1 at the falling edge
of each clock 2 (CL2) pulse.
Data Shifter
The data shifter shifts the destinations of display
data output, when necessary.
1159
HD66120T
Pin Description
Symbol
V
CC
GND1, GND2
V
LCD1
, V
LCD2
V1L, V1R
V2L, V2R
V3L, V3R
V4L, V4R
CL1
CL2
M
D
0
–D
7
SHL
EIO1, EIO2
DISP
BS
Y
1
–Y
240
Pin No.
247
246, 264
241, 269
242, 268
245, 265
243, 267
244, 266
260
258
262
250–257
263
261, 249
259
248
1–240
Pin Name
V
CC
GND1, GND2
V
LCD1
, V
LCD2
V1L, V1R
V2L, V2R
V3L, V3R
V4L, V4R
Clock 1
Clock 2
M
Data 0–data 7
Shift left
Enable IO 1,
enable IO 2
Display off
Bus select
Y
1
–Y
240
Input/Output
—
—
—
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input/output
Input
Input
Output
Classification
Power supply
Power supply
Power supply
Power supply
Power supply
Power supply
Power supply
Control signal
Control signal
Control signal
Control signal
Control signal
Control signal
Control signal
Control signal
LCD drive output
1160
单片机
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