D at a S he e t, R ev . 0 .8 5 , Ap r . 2 00 4
H YS72 T 640 00 [G/H ]R - x -A
(5 12 M B y t e )
H YS72 T 128 00 0[ G/H] R-x-A
( 1 G B y t e )
H YS72 T 128 02 0[ G/H] R-x-A
( 1 G B y t e )
H YS72 T 256 02 0[ G/H] R-x-A
( 2 G B y t e )
H YS72 T 256 22 0[ G/H] R-x-A
( 2 G B y t e )
DDR 2 Reg istered Me mo ry Mo dul es
M em or y P r od uc t s
N e v e r
s t o p
t h i n k i n g .
HYS72T[256/128/64][0/2][0/2]0[G/H]R-[5/3.7]-A
Preliminary Data Sheet Rev. 0.85 (Apr. 2004)
Low Profile 240-pin Registered DDR2 SDRAM Modules Datasheet
512 MByte, 1 GByte & 2 GByte Modules
PC2-3200R, PC2-4300R
• 240-pin Registered 8-Byte ECC Dual-In-Line
DDR2 SDRAM Module for PC, Workstation
and Server main memory applications
• One rank 64Mb x 72, 128Mb x 72 and
two ranks 128Mb
×
72 and 256Mb x 72
organizations
• JEDEC standard Double Data Rate 2
Synchronous DRAMs (DDR2 SDRAMs) with
+ 1.8 V (± 0.1 V) power supply
• 512MB and 1 GB modulesModules built with
512Mb DDR2 SDRAMs in 60-ball FBGA
chipsize packages
• Two versions of 2 GB modules
built with 63-ball FBGA dual die chipsiz
e packages
(
2 x 512Mb components) or 60-ball FBGA packages
Performance:
Speed Grade Indicator
Component Speed Grade on Module
Module Speed Grade
Max. Clock Frequency @ CL = 3
Max. Clock Frequency@ CL = 4 & 5
–5
DDR2–400
PC2–3200R
200
200
–3.7
DDR2–533
PC2–4300R
200
266
MHz
MHz
Unit
• Programmable CAS Latencies (3, 4 & 5),
Burst Length (4 & 8) and Burst Type.
• Auto Refresh and Self Refresh
• All inputs and outputs SSTL_1.8 compatible
• Re-drive for all input signals using register
and PLL devices.
• OCD (Off-Chip Driver Impedance
Adjustment) and ODT (On-Die Termination)
• Serial Presence Detect with E
2
PROM
• Low Profile Modules form factor:
133.35 mm x 30,00 mm (MO-237)
• Based on JEDEC standard reference card
designs
1.0 Description
The INFINEON HYS72Taaabcd[G/H]R module family are low profile Registered DIMM modules
with 30,00 mm height based on DDR2 technology. DIMMs are available in 64M x 72 (512MByte),
128M x 72 (1GByte) and 256M x 72 (2GByte) organisation and density, intended for mounting into
240 pin connector sockets.
The memory array is designed with 512Mb Double Data Rate (DDR2) Synchronous DRAMs for
ECC applications. All control and address signals are re-driven on the DIMM using register devices
and a PLL for the clock distribution. This reduces capacitive loading to the system bus, but adds one
cycle to the SDRAM timing. Decoupling capacitors are mounted on the PCB board, which provide
a proper voltage supply impedance over the whole frequency range of operations as number and
values are accordant to the JEDEC specification. The DIMMs feature serial presence detect based
on a serial E
2
PROM device using the 2-pin I
2
C protocol. The first 128 bytes are programmed with
configuration data and the second 128 bytes are available to the customer.
2
Rev. 0.85, 2004-04
HYS72T[256/128/64][0/2][0/2]0[G/H]R-[5/3.7]-A
Registered DDR2 SDRAM Modules
1.1 Ordering Information
Product Type
PC2-3200
(DDR2-400)
HYS72T64000GR-5-A
HYS72T128020GR-5-A
HYS72T128000GR-5-A
HYS72T256220GR-5-A
HYS72T256020GR-5-A
PC2-4300
(DDR2-533)
HYS72T64000GR-3.7-A
HYS72T128020GR-3.7-A
HYS72T128000GR-3.7-A
HYS72T256020GR-3.7-A
PC2-3200
(DDR2-400)
HYS72T64000HR-5-A
HYS72T128020HR-5-A
HYS72T128000HR-5-A
HYS72T256220HR-5-A
HYS72T256020HR-5-A
PC2-4300
(DDR2-533)
HYS72T64000HR-3.7-A
HYS72T128020HR-3.7-A
HYS72T128000HR-3.7-A
HYS72T256020HR-3.7-A
PC2-4300R-444-11-A
PC2-4300R-444-11-B
PC2-4300R-444-11-C
PC2-4300R-444-11
one rank 512 MB Reg. DIMM
two ranks 1024 MB Reg.DIMM
one rank 1024 MB Reg. DIMM
two ranks 2048 MB Reg. DIMM
512 Mbit (x8)
512 Mbit (x8)
512 Mbit (x4)
512 Mbit (x4)
PC2-3200R-333-11-A
PC2-3200R-333-11-B
PC2-3200R-333-11-C
PC2-3200R-333-11
PC2-3200R-333-11
one rank 512 MB Reg. DIMM
two ranks 1024 MB Reg.DIMM
one rank 1024 MB Reg. DIMM
two ranks 2048 MB Reg. DIMM
two ranks 2048 MB Reg. DIMM
512 Mbit (x8)
512 Mbit (x8)
512 Mbit (x4)
512 Mbit (x4)
512 Mbit (x4)
PC2-4300R-444-11-A
PC2-4300R-444-11-B
PC2-4300R-444-11-C
PC2-4300R-444-11
one rank 512 MB Reg. DIMM
two ranks 1024 MB Reg.DIMM
one rank 1024 MB Reg. DIMM
two ranks 2048 MB Reg. DIMM
512 Mbit (x8)
512 Mbit (x8)
512 Mbit (x4)
512 Mbit (x4)
PC2-3200R-333-11-A
PC2-3200R-333-11-B
PC2-3200R-333-11-C
PC2-3200R-333-11
PC2-3200R-333-11
one rank 512 MB Reg. DIMM
two ranks 1024 MB Reg.DIMM
one rank 1024 MB Reg. DIMM
two ranks 2048 MB Reg. DIMM
two ranks 2048 MB Reg. DIMM
512 Mbit (x8)
512 Mbit (x8)
512 Mbit (x4)
512 Mbit (x4)
512 Mbit (x4)
Compliance Code
Description
SDRAM Technology
Notes:
1. For all INFINEON DDR2 module and component nomenclature see section 8 of this data sheet.
2. The Compliance Code is printed on the module label and describes the speed grade, e. g. “PC2-4300R-444-11-C”, where
4300R means Registered modules with 4.26 GB/sec Module Bandwidth and “444-11” means CAS latency = 4, trcd latency
= 4 and trp latency = 4 using the latest JEDEC SPD Revision 1.1 and produced on the Raw Card “C”.
1.2 Address Format
Product Type
HYS72T64000GR
HYS72T64000HR
HYS72T128020GR
HYS72T128020HR
HYS72T128000GR
HYS72T128000HR
HYS72T256220GR
HYS72T256220HR
HYS72T256020GR
HYS72T256020HR
DIMM Density Organization DIMM Ranks SDRAMs # of SDRAMs # of row/bank/
column bits
512 MB
1024 MB
1024 MB
2048 MB
2048 MB
64Mb
×
72
2 x 64Mb
×
72
128Mb x 72
2 x 128Mb
×
72
2 x 128Mb
×
72
1
2
1
2
2
(512Mb)
64Mb
×
8
(512Mb)
64Mb
×
8
(512Mb)
128Mb
×
4
(512Mb)
128Mb
×
4
(512Mb)
128Mb
×
4
9
18
18
36
36
14/2/10
14/2/10
14/2/11
14/2/11
14/2/11
Data Sheet
Preliminary
3
Rev. 0.85, 2004-04
HYS72T[256/128/64][0/2][0/2]0[G/H]R-[5/3.7]-A
Registered DDR2 SDRAM Modules
1.3 Components on Modules and RawCard
DIMM
Density
512 MB
1024 MB
1024 MB
2048 MB
2048 MB
DRAM components
reference datasheet
HYB18T512800AC
HYB18T512800AF
HYB18T512800AC
HYB18T512800AF
HYB18T512400AC
HYB18T512400AF
HYB18T512400AC
HYB18T512400AF
HYB18T512400AC
HYB18T512400AF
PLL
1:10, 1.8V, CU877
1:10, 1.8V, CU877
1:10, 1.8V, CU877
tbd.
tbd.
Register
1:1 25-bit 1.8V SSTU32864
1:2 14-bit 1.8V SSTU32864
1:2 14-bit 1.8V SSTU32864
tbd.
tbd.
Raw Card
A
B
C
tbd.
tbd.
For a detailed description of all functionalities of the DRAM components on these modules see the referenced component data
sheet
1.4 Pin Definition and Function
Pin Name
A[13:0]
A11, A[9:0]
A10/AP
BA[1:0]
CK0
CK0
RAS
CAS
WE
CS[1:0]
CKE[1:0]
ODT[1:0]
DQ[63:0]
Description
Row Address Inputs
Column Address Inputs
4)
Pin Name
CB[7:0]
DQS[8:0]
DM[8:0] /
DQS[17:9]
DQS[17:0]
SCL
SDA
SA[2:0]
V
DD
V
REF
V
SS
V
DDSPD
1) 3)
Description
DIMM ECC Check Bits
SDRAM low data strobes
SDRAM low data mask/
high data strobes
SDRAM differential data strobes
Serial bus clock
Serial bus data line
slave address select
Power (+ 1.8 V)
I/O reference supply
Ground
EEPROM power supply
Register and PLL control pin
2)
No connection
Column Address Input for Auto-
Precharge
SDRAM Bank Selects
Clock input
(positive line of differential pair)
Clock input
(negative line of differential pair)
Row Address Strobe
Column Address Strobe
Read/Write Input
Chip Selects
3)
Clock Enable
3)
Active termination control lines
Data Input/Output
RESET
NC
1) Active termination only applies to DQ, DQS, DQS and DM signals
2) When low, all register outputs will be driven low and the PLL clocks to the DRAM and registers will be set to low levels (the
PLL will remain synchronized with the input clock
3) CS1, ODT1 and CKE1 are used on dual rank modules only
4) Column address A11 is used on modules based on x4 organised 512Mb DDR2 components only.
Data Sheet
Preliminary
4
Rev. 0.85, 2004-04
HYS72T[256/128/64][0/2][0/2]0[G/H]R-[5/3.7]-A
Registered DDR2 SDRAM Modules
1.5 Pin Configuration
PIN#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
Symbol
VREF
VSS
DQ0
DQ1
VSS
DQS0
DQS0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1
DQS1
VSS
RESET
NC
VSS
DQ10
DQ11
VSS
DQ16
DQ17
VSS
DQS2
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DQS3
DQS3
VSS
DQ26
DQ27
PIN#
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
Symbol
VSS
DQ4
DQ5
VSS
DM0, DQS9
DQS9
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1, DQS10
DQS10
VSS
NC
NC
VSS
DQ14
DQ15
VSS
DQ20
DQ21
VSS
DM2, DQS11
DQS11
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DM3, DQS12
DQS12
VSS
DQ30
DQ31
VSS
PIN#
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
Symbol
A4
VDDQ
A2
VDD
KEY
VSS
VSS
VDD
NC
VDD
A10/AP
BA0
VDDQ
WE
CAS
VDDQ
CS1
ODT1
VDDQ
VSS
DQ32
DQ33
VSS
DQS4
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DQS5
DQS5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
PIN#
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
Symbol
VDDQ
A3
A1
VDD
KEY
CK0
CK0
VDD
A0
VDD
BA1
VDDQ
RAS
CS0
VDDQ
ODT0
A13
VDD
VSS
DQ36
DQ37
VSS
DM4, DQS13
DQS13
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DM5, DQS14
DQS14
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
Data Sheet
Preliminary
5
Rev. 0.85, 2004-04
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