10 MHz to 100 and 133 MHz operating range, compatible
with CPU and PCI bus frequencies
Zero input-output propagation delay
Multiple low skew outputs
❐
Output-output skew less than 250 ps
❐
Device-device skew less than 700 ps
❐
One input drives five outputs (CY23S05)
❐
One input drives nine outputs, grouped as 4 + 4 + 1
(CY23S09)
Less than 200 ps cycle-to-cycle jitter is compatible with
Pentium
®
based systems
Test mode to bypass PLL (CY23S09 only, see
Select Input
Decoding for CY23S09
on page 2)
Available in space saving 16-pin, 150-mil SOIC, 4.4 mm
TSSOP, and 150-mil SSOP ( CY23S09) or 8-pin, 150-mil
SOIC package (CY23S05)
3.3V operation, advanced 0.65μ CMOS technology
Spread Aware
MHz frequencies and have higher drive than the -1 devices. All
parts have on-chip PLLs that lock to an input clock on the REF
pin. The PLL feedback is on-chip and is obtained from the
CLKOUT pad.
The CY23S09 has two banks of four outputs each, which can be
controlled by the select inputs as shown in the Select Input
Decoding table on
Select Input Decoding for CY23S09
on page
2. If all output clocks are not required, Bank B can be
three-stated. The select inputs also allow the input clock to be
directly applied to the outputs for chip and system testing
purposes.
The CY23S09 and CY23S05 PLLs enter a power down mode
when there are no rising edges on the REF input. In this state,
the outputs are three-stated and the PLL is turned off, resulting
in less than 12.0
μA
of current draw (for commercial temperature
devices) and 25.0
μA
(for industrial temperature devices). The
CY23S09 PLL shuts down in one additional case, as shown in
the
Select Input Decoding for CY23S09
on page 2.
Multiple CY23S09 and CY23S05 devices can accept the same
input clock and distribute it. In this case, the skew between the
outputs of two devices is guaranteed to be less than 700 ps.
All outputs have less than 200 ps of cycle-to-cycle jitter. The input
to output propagation delay on both devices is guaranteed to be
less than 350 ps; the output to output skew is guaranteed to be
less than 250 ps.
The CY23S05 and CY23S09 is available in two different config-
urations, as shown in the
Ordering Information
on page 6. The
CY23S05-1 and CY23S09-1 is the base part. The CY23S05-1H
and CY23S09-1H is the high drive version of the -1, and its rise
and fall times are much faster than -1.
■
■
■
■
■
Functional Description
The CY23S09 is a low cost 3.3V zero delay buffer designed to
distribute high speed clocks and is available in a 16-pin SOIC
package. The CY23S05 is an 8-pin version of the CY23S09. It
accepts one reference input, and drives out five low skew clocks.
The -1H versions of each device operate at up to 100 and 133
Logic Block Diagram
Cypress Semiconductor Corporation
Document Number: 38-07296 Rev. *D
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised October 22, 2008
[+] Feedback
CY23S09, CY23S05
Select Input Decoding for CY23S09
S2
0
0
1
1
S1
0
1
0
1
CLOCK A1–A4
Three-state
Driven
Driven
Driven
CLOCK B1–B4
Three-state
Three-state
Driven
Driven
CLKOUT
[1]
Driven
Driven
Driven
Driven
Output Source
PLL
PLL
Reference
PLL
PLL Shut-down
N
N
Y
N
Zero Delay and Skew Control
All outputs must be uniformly loaded to achieve Zero Delay
between the input and output. Because the CLKOUT pin is the
internal feedback to the PLL, its relative loading can adjust the
input-output delay. This is shown in the above graph.
For applications requiring zero input-output delay, all outputs,
including CLKOUT, must be equally loaded. Even if CLKOUT is
not used, it must have a capacitive load equal to that on other
outputs, to obtain zero input-output delay. If input to output delay
adjustments are required, use the above graph to calculate
loading differences between the CLKOUT pin and other outputs.
For zero output-output skew, be sure to load all outputs equally.
For further information, refer to the application note “CY23S05
and CY23S09 as PCI and SDRAM Buffers.”
Spread Aware
Many systems being designed now use a technology called
Spread Spectrum Frequency Timing Generation. Cypress is one
of the pioneers of SSFTG development and designed this
product so as not to filter off the Spread Spectrum feature of the
Reference input, assuming it exists. When a zero delay buffer is
not designed to pass the SS feature through, the result is a signif-
icant amount of tracking skew, which may cause problems in
systems requiring synchronization.
For more details on Spread Spectrum timing technology, please
see the Cypress application note
AN1278,
EMI Suppression
Techniques with Spread Spectrum Frequency Timing Generator
(SSFTG) ICs.
Pin Configurations
Figure 1. Pin Diagram - CY23S09
Figure 2. Pin Diagram - CY23S05
Note
1. This output is driven and has an internal feedback for the PLL. The load on this output can be adjusted to change the skew between the reference and output.
Document Number: 38-07296 Rev. *D
Page 2 of 9
[+] Feedback
CY23S09, CY23S05
Pin Description for CY23S09
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
REF
[2]
CLKA1
[3]
CLKA2
[3]
V
DD
GND
CLKB1
[3]
CLKB2
[3]
S2
[4]
S1
[4]
CLKB3
[3]
CLKB4
[3]
GND
V
DD
CLKA3
[3]
CLKA4
[3]
CLKOUT
[3]
Signal
Buffered clock output, bank A
Buffered clock output, bank A
3.3V supply
Ground
Buffered clock output, bank B
Buffered clock output, bank B
Select input, bit 2
Select input, bit 1
Buffered clock output, bank B
Buffered clock output, bank B
Ground
3.3V supply
Buffered clock output, bank A
Buffered clock output, bank A
Buffered output, internal feedback on this pin
Description
Input reference frequency, 5V tolerant input
Pin Description for CY23S05
Pin
1
2
3
4
5
6
7
8
REF
[2]
CLK2
[3]
CLK1
[3]
GND
CLK3
[3]
V
DD
CLK4
[3]
CLKOUT
[3]
Signal
Buffered clock output
Buffered clock output
Ground
Buffered clock output
3.3V supply
Buffered clock output
Buffered clock output, internal feedback on this pin
Description
Input reference frequency, 5V tolerant input
Notes
2. Weak pull-down.
3. Weak pull-down on all outputs.
4. Weak pull-up on these inputs.
Document Number: 38-07296 Rev. *D
Page 3 of 9
[+] Feedback
CY23S09, CY23S05
Maximum Ratings
Supply Voltage to Ground Potential................–0.5V to +7.0V
DC Input Voltage (Except REF) ............ –0.5V to V
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