DATASHEET
PCI-EXPRESS GEN1 CLOCK SOURCE
Description
The ICS557-03 is a spread spectrum clock generator that
supports PCI-Express Gen 1 and Ethernet requirements.
The device is used for PC or embedded systems to
substantially reduce electromagnetic interference (EMI).
The device provides two differential (HCSL) spread
spectrum outputs. The spread type and amount are
configured via select pin. Using IDT’s patented
Phase-Locked Loop (PLL) techniques, the device takes a
25 MHz crystal input and produces two pairs of differential
outputs at 25 MHz, 100 MHz, 125 MHz or 200 MHz clock
frequencies for HCSL, and 25 MHz or 100 MHz for LVDS.
ICS557-03
Features
•
Packaged in 16-pin TSSOP
•
RoHS 5 (green) or RoHS 6 (green and lead free)
compliant packaging
•
•
•
•
•
•
Supports HCSL or LVDS output levels
Operating voltage of 3.3 V
Input frequency of 25 MHz
Jitter 60 ps (cycle-to-cycle)
Spread Spectrum capability
Industrial and commercial temperature ranges
Block Diagram
VDD
2
SS1:SS0
S1:S0
2
CLK0
Control
Logic
Phase Lock Loop
CLK1
CLK1
CLK0
2
X1/ICLK
25 MHz
crystal or clock X2
Optional tuning crystal
capacitors
Clock
Buffer/
Crystal
Oscillator
2
GND
OE
Rr(IREF)
IDT™ / ICS™
PCI-EXPRESS GEN1 CLOCK SOURCE
1
ICS557-03
REV Q 051310
ICS557-03
PCI-EXPRESS GEN1 CLOCK SOURCE
PCIE SSCG
Pin Assignment
S0
S1
SS0
X1/ICLK
X2
OE
GNDXD
SS1
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VDDXD
CLK0
CLK0
GNDODA
VDDODA
CLK1
CLK1
IREF
Output Select Table 1 (MHz)
S1
0
0
1
1
S0
0
1
0
1
CLK(1:0), CLK(1:0)
25M
100M
125M
200M
Spread Selection Table 2
SS1
0
0
1
1
SS0
0
1
0
1
Spread%
No Spread
Down -0.5
Down -0.75
No Spread
16-pin (173 mil) TSSOP
Pin Descriptions
Pin
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Pin
Name
S0
S1
SS0
X1/ICLK
X2
OE
GNDXD
SS1
IREF
CLK1
CLK1
VDDODA
GNDODA
CLK0
CLK0
VDDXD
Pin
Type
Input
Input
Input
Input
Input
Power
Input
Pin Description
Select pin 0. See Table1. Internal pull-up resistor.
Select pin 1. See Table 1. Internal pull-up resistor.
Spread Select pin 0. See Table 2. Internal pull-up resistor.
Crystal or clock input. Connect to a 25 MHz crystal or single ended clock.
Output enable. Tri-states outputs and device is not shut down. Internal
pull-up resistor.
Connect to ground.
Spread Select pin 1. See Table 2. Internal pull-up resistor.
Output Crystal connection. Leave unconnected for clock input.
Output Precision resistor attached to this pin is connected to the internal current
reference.
Output HCSL complimentary clock output 1.
Output HCSL true clock output 1.
Power
Power
Connect to voltage supply +3.3 V for output driver and analog circuits
Connect to ground.
Output HCSL complimentary clock output 0.
Output HCSL true clock output 0.
Power
Connect to voltage supply +3.3 V for crystal oscillator and digital circuit.
IDT™ / ICS™
PCI-EXPRESS GEN1 CLOCK SOURCE
2
ICS557-03
REV Q 051310
ICS557-03
PCI-EXPRESS GEN1 CLOCK SOURCE
PCIE SSCG
Applications Information
External Components
A minimum number of external components are required for
proper operation.
Output Structures
IREF
=2.3 mA
6*IREF
Decoupling Capacitors
Decoupling capacitors of 0.01
µF
should be connected
between each VDD pin and the ground plane, as close to
the VDD pin as possible. Do not share ground vias between
components. Route power from power source through the
capacitor pad and then into ICS pin.
Crystal
A 25 MHz fundamental mode parallel resonant crystal
should be used. This crystal must have less than 300 ppm
of error across temperature in order for the ICS557-03 to
meet PCI Express specifications.
R
R
475
Ω
See Output Termination
Sections - Pages 3 ~ 5
Crystal Capacitors
Crystal capacitors are connected from pins X1 to ground
and X2 to ground to optimize the accuracy of the output
frequency.
C
L
= Crystal’s load capacitance in pF
Crystal Capacitors (pF) = (C
L
- 8) * 2
For example, for a crystal with a 16 pF load cap, each
external crystal cap would be 16 pF. (16-8)*2=16.
Current Source (Iref) Reference Resistor - R
R
If board target trace impedance (Z) is 50Ω then R
R
= 475Ω
,
(1%), providing IREF of 2.32 mA. The output current (I
OH
) is
equal to 6*IREF.
Output Termination
The PCI-Express differential clock outputs of the ICS557-03
are open source drivers and require an external series
resistor and a resistor to ground. These resistor values and
their allowable locations are shown in detail in the
PCI-Express Layout Guidelines
section.
The ICS557-03 can also be configured for LVDS compatible
voltage levels. See the
LVDS Compatible Layout
Guidelines
section.
General PCB Layout Recommendations
For optimum device performance and lowest output phase
noise, the following guidelines should be observed.
1. Each 0.01µF decoupling capacitor should be mounted on
the component side of the board as close to the VDD pin as
possible.
2. No vias should be used between decoupling capacitor
and VDD pin.
3. The PCB trace to VDD pin should be kept as short as
possible, as should the PCB trace to the ground via.
Distance of the ferrite bead and bulk decoupling from the
device is less critical.
4. An optimum layout is one with all components on the
same side of the board, minimizing vias through other signal
layers (any ferrite beads and bulk decoupling capacitors can
be mounted on the back). Other signal traces should be
routed away from the ICS557-03.This includes signal traces
just underneath the device, or on layers adjacent to the
ground plane layer used by the device.
IDT™ / ICS™
PCI-EXPRESS GEN1 CLOCK SOURCE
3
ICS557-03
REV Q 051310
ICS557-03
PCI-EXPRESS GEN1 CLOCK SOURCE
PCIE SSCG
PCI-Express Layout Guidelines
Common Recommendations for Differential Routing
L1 length, Route as non-coupled 50 ohm trace.
L2 length, Route as non-coupled 50 ohm trace.
L3 length, Route as non-coupled 50 ohm trace.
R
S
R
T
Differential Routing on a Single PCB
L4 length, Route as coupled
microstrip
100 ohm differential trace.
L4 length, Route as coupled
stripline
100 ohm differential trace.
Differential Routing to a PCI Express Connector
L4 length, Route as coupled
microstrip
100 ohm differential trace.
L4 length, Route as coupled
stripline
100 ohm differential trace.
Dimension or Value
0.5 max
0.2 max
0.2 max
33
49.9
Dimension or Value
2 min to 16 max
1.8 min to 14.4 max
Dimension or Value
0.25 to 14 max
0.225 min to 12.6 max
Unit
inch
inch
inch
ohm
ohm
Unit
inch
inch
Unit
inch
inch
PCI-Express Device Routing
L1
R
S
L1’
R
S
L2
L2’
R
T
L3’
R
T
L3
L4
L4’
ICS557-03
Output
Clock
PCI-Express
Load or
Connector
Typical PCI-Express (HCSL) Waveform
700 mV
0
t
OR
500 ps
500 ps
t
OF
0.525 V
0.175 V
0.525 V
0.175 V
IDT™ / ICS™
PCI-EXPRESS GEN1 CLOCK SOURCE
4
ICS557-03
REV Q 051310
ICS557-03
PCI-EXPRESS GEN1 CLOCK SOURCE
PCIE SSCG
LVDS Compatible Layout Guidelines
LVDS Recommendations for Differential Routing
L1 length, Route as non-coupled 50 ohm trace.
L2 length, Route as non-coupled 50 ohm trace.
R
P
R
Q
R
T
Dimension or Value
0.5 max
0.2 max
100
100
150
Unit
inch
inch
ohm
ohm
ohm
LVDS Device Routing
L1
R
Q
L1’
L3
L3’
R
P
R
T
ICS557-03
Clock
Output
L2’
L2
R
T
LVDS
Device
Load
Typical LVDS Waveform
1325 mV
1000 mV
t
OR
500 ps
500 ps
t
OF
1250 mV
1150 mV
1250 mV
1150 mV
IDT™ / ICS™
PCI-EXPRESS GEN1 CLOCK SOURCE
5
ICS557-03
REV Q 051310
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