DS5000(T)
Soft Microcontroller Module
www.maxim-ic.com
FEATURES
8-Bit 8051-Compatible Microcontroller
Adapts to Task at Hand
8 or 32 kbytes of Nonvolatile RAM for
Program and/or Data Memory Storage
Initial Downloading of Software in End
System via On-Chip Serial Port
Capable of Modifying Its Own Program
and/or Data Memory in End Use
Crashproof Operation
Maintains All Nonvolatile Resources for 10
Years in the Absence of V
CC
at Room
Temperature
Power-Fail Reset
Early Warning Power-Fail Interrupt
Watchdog Timer
Software Security Feature
Executes Encrypted Software to Prevent
Unauthorized Disclosure
On-Chip, Full-Duplex Serial I/O Ports
Two On-Chip Timer/Event Counters
32 Parallel I/O Lines
Compatible with Industry Standard 8051
Instruction Set and Pinout
Optional Permanently Powered Real-Time
Clock (DS5000T)
PIN ASSIGNMENT
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
RST
RXD P3.0
TXD P3.1
INT0 P3.2
INT1 P3.3
T0 P3.4
T1 P3.5
WR P3.6
RD P3.7
XTAL2
XTAL1
GND
1
40
2
39
3
DS5000(T)
38
4
37
5
36
6
35
7
34
8
33
9
32
10
31
11
30
12
29
13
28
14
27
15
26
16
25
17
24
18
23
19
22
20
21
V
CC
P0.0 AD0
P0.1 AD1
P0.2 AD2
P0.3 AD3
P0.4 AD4
P0.5 AD5
P0.6 AD6
P0.7 AD7
EA
ALE
PSEN
P2.7 A15
P2.6 A14
P2.5 A13
P2.4 A12
P2.3 A11
P2.2 A10
P2.1 A9
P2.0 A8
40-Pin Encapsulated Package
DESCRIPTION
The DS5000(T) Soft Microcontroller Module is a fully 8051-compatible 8-bit CMOS microcontroller that
offers “softness” in all aspects of its application. This is accomplished through the comprehensive use of
nonvolatile technology to preserve all information in the absence of system V
CC
. The internal
program/data memory space is implemented using either 8 or 32 kbytes of nonvolatile CMOS SRAM.
Furthermore, internal data registers and key configuration registers are also nonvolatile. An optional real-
time clock (RTC) gives permanently powered timekeeping. The clock keeps time to a hundredth of a
second using an on-board crystal.
Note:
This data sheet provides ordering information, pinout, and electrical specifications. Refer to the
Secure Microcontroller User’s Guide
for operating information.
Note:
Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here:
www.maxim-ic.com/errata.
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REV: 070706
DS5000(T)
ORDERING INFORMATION
PART
DS5000-32-16
DS5000-32-16+
DS5000T-32-16
DS5000T-32-16+
+
Denotes a lead-free package.
RAM SIZE (kB)
32
32
32
32
MAX CRYSTAL
SPEED (MHz)
16
16
16
16
TIMEKEEPING?
No
No
Yes
Yes
DS5000(T) BLOCK DIAGRAM
Figure 1
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DS5000(T)
PIN DESCRIPTION
PIN
1–8
9
10
11
12
13
14
15
16
17
18, 19
20
21–28
NAME
P1.0–P1.7
RST
P3.0/RXD
P3.1/TXD
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1
P3.6/WR
P3.7/RD
XTAL2,
XTAL1
GND
P2.0–P2.7/
A8–A15
General-Purpose I/O Port 1
Active-High Reset Input. A logic 1 applied to this pin will activate a reset state.
This pin is pulled down internally so this pin can be left unconnected if not used.
General-Purpose I/O Port Pin 3.0/Receive Signal for On-Board UART. This pin
should not be connected directly to a PC COM port.
General-Purpose I/O Port Pin 3.1/Transmit Signal for On-Board UART. This pin
should not be connected directly to a PC COM port.
General-Purpose I/O Port Pin 3.2/Active-Low External Interrupt 0
General-Purpose I/O Port Pin 3.3/Active-Low External Interrupt 1
General-Purpose I/O Port Pin 3.4/Timer 0 Input
General-Purpose I/O Port Pin 3.5/Timer 1 Input
General-Purpose I/O Port Pin 3.6/Active-Low Write Strobe for Expanded Bus
Operation
General-Purpose I/O Port Pin 3.7/Active-Low Read Strobe for Expanded Bus
Operation
Crystal Connection. Used to connect an external crystal to the internal oscillator.
XTAL1 is the input to an inverting amplifier and XTAL2 is the output.
Logic Ground
General-Purpose I/O Port 2/MSB of the Expanded Address Bus
Active-Low Program Store Enable. Used to enable an external program memory
when using the expanded bus. It is normally an output and should be unconnected
if not used.
PSEN
also is used to invoke the bootstrap loader. At this time,
PSEN
is
pulled down externally. This should only be done once the DS5000(T) is already in
a reset state. The device that pulls down should be open drain since it must not
interfere with
PSEN
under normal operation.
Address Latch Enable. Used to demultiplex the multiplexed expanded address/data
bus on Port 0. This pin is normally connected to the clock input on a ’373 type
transparent latch. When using a parallel programmer, this pin also assumes the
PROG
function for programming pulses.
Active-Low External Access. This pin forces the DS5000(T) to behave like an
8031. No internal memory (or clock) is available when this pin is at a logic low.
Since this pin is pulled down internally, it should be connected to +5V to use NV
RAM. In a parallel programmer, this pin also serves as V
PP
for super voltage
pulses.
General-Purpose I/O Port 0/Multiplexed Expanded Address/Data Bus. This port is
open drain and cannot drive a logic 1. It requires external pullups. When used in
the multiplexed expanded address data/bus mode, this pin does not require pullups.
+5V Power Supply
FUNCTION
29
PSEN
30
ALE
31
EA
32-39
40
P0.7–P0.0/
AD7–AD0
V
CC
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DS5000(T)
INSTRUCTION SET
The DS5000(T) executes an instruction set which is object code-compatible with the industry standard
8051 microcontroller. As a result, software development packages that have been written for the 8051,
including cross-assemblers, high-level language compilers, and debugging tools, are compatible with the
DS5000(T).
A complete description for the DS5000(T) instruction set is available in
Secure Microcontroller User’s
Guide.
MEMORY ORGANIZATION
Figure 2 illustrates the address spaces, which are accessed by the DS5000(T). As illustrated in the figure,
separate address spaces exist for program and data memory. Since the basic addressing capability of the
machine is 16 bits, a maximum of 64 kbytes of program memory and 64 kbytes of data memory can be
accessed by the DS5000(T) CPU. The 8- or 32-kbyte RAM area inside of the DS5000(T) can be used to
contain both program and data memory.
The real-time clock (RTC) in the DS5000T is reached in the memory map by setting a SFR bit. The
MCON.2 bit (ECE2) is used to select an alternate data memory map. While ECE2 = 1, all MOVXs will
be routed to this alternate memory map. The RTC is a serial device that resides in this area. A full
description of the RTC access and example software is given in the
Secure Microcontroller User’s Guide.
If the ECE2 bit is set on a DS5000 without a timekeeper, the MOVXs will simply go to a nonexistent
memory. Software execution would not be affected otherwise.
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DS5000(T)
DS5000(T) LOGICAL ADDRESS SPACES
Figure 2
PROGRAM LOADING
The Program Load Modes allow initialization of the NV RAM Program/Data Memory. This initialization
may be performed in one of two ways:
1. Serial Program Loading that can perform Bootstrap Loading of the DS5000(T). This feature allows
the loading of the application program to be delayed until the DS5000(T) is installed in the end
system. Dallas Semiconductor strongly recommends the use of serial program loading because of its
versatility and ease of use.
2. Parallel Program Load cycles that perform the initial loading from parallel address/data information
presented on the I/O port pins. This mode is timing-set compatible with the 8751H microcontroller
programming mode.
The DS5000(T) is placed in its Program Load configuration by simultaneously applying a logic 1 to the
RST pin and forcing the
PSEN
line to a logic 0 level. Immediately following this action, the DS5000(T)
will look for a parallel Program Load pulse, or a serial ASCII carriage return (0DH) character received at
9600, 2400, 1200, or 300 bps over the serial port.
The hardware configurations used to select these modes of operation are illustrated in Figure 3.
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