DATASHEET
EL1881
Sync Separator, Low Power
The EL1881 video sync separator is manufactured using
Elantec’s high performance analog CMOS process. This
device extracts sync timing information from both standard
and non-standard video input. It provides composite sync,
vertical sync, burst/back porch timing, and odd/even field
detection. Fixed 70mV sync tip slicing provides sync edge
detection when the video input level is between 0.5V
P-P
and
-2V
P-P
(sync tip amplitude 143mV to 572mV). A single
external resistor sets all internal timing to adjust for various
video standards. The composite sync output follows video in
sync pulses and a vertical sync pulse is output on the rising
edge of the first vertical serration following the vertical
pre-equalizing string. For non-standard vertical inputs, a
default vertical pulse is output when the vertical signal stays
low for longer than the vertical sync default delay time. The
odd/even output indicates field polarity detected during the
vertical blanking interval. The EL1881 is plug-in compatible
with the industry-standard LM1881 and can be substituted
for that part in 5V applications with lower required supply
current.
The EL1881 is available in the 8 Ld PDIP and SOIC
packages and is specified for operation over the full -40°C to
+85°C temperature range
FN7018
Rev 2.00
September 15, 2011
Features
• NTSC, PAL, SECAM, non-standard video sync separation
• Fixed 70mV slicing of video input levels from 0.5V
P-P
to
2V
P-P
• Low supply current - 1.5mA typ.
• Single +5V supply
• Composite, vertical sync output
• Odd/even field output
• Burst/back porch output
• Available in 8 Ld PDIP and SOIC packages
• Pb-free available (RoHS Compliant)
Applications
• Video amplifiers
• PCMCIA applications
• A/D drivers
• Line drivers
• Portable computers
• High-speed communications
Pinout
EL1881
(8 LD PDIP, SOIC)
TOP VIEW
COMPOSITE SYNC OUT 1
COMPOSITE VIDEO IN 2
VERTICAL SYNC OUT 3
GND
4
8
V
DD
5V
• RGB applications
• Broadcast equipment
• Active filtering
7 ODD/EVEN OUTPUT
6
R
SET
Demo Board
A dedicated demo board is available.
5 BUST/BACK
PORCH OUTPUT
FN7018 Rev 2.00
September 15, 2011
Page 1 of 13
EL1881
Pin Descriptions
PIN NUMBER
1
2
3
4
5
6
7
8
NOTE:
1. R
SET
must be a 1% resistor
PIN NAME
Composite Sync
Out
Composite Video
In
Vertical Sync Out
GND
Burst/Back Porch
Output
R
SET
(Note 1)
Odd/Even Output
VDD 5V
PIN FUNCTION
Composite sync pulse output; sync pulses start on a falling edge and end on a rising edge
AC coupled composite video input; sync tip must be at the lowest potential (positive picture phase)
Vertical sync pulse output; the falling edge of vert sync is the start of the vertical period
Supply ground
Burst/back porch output; low during burst portion of composite video
An external resistor to ground sets all internal timing; a 681k 1% resistor will provide correct timing for
NTSC signals
Odd/even field output; high during odd fields, low during even fields; transitions occur at start of vert sync
pulse
Positive supply (5V)
Ordering Information
PART NUMBER
EL1881CN
EL1881CS
EL1881CS-T7 (Note 2)
EL1881CSZ (Notes 3, 4)
EL1881CSZ-T7 (Notes 2, 3, 4)
EL1881CSZ-T13 (Notes 2, 3, 4))
NOTES:
2. Please refer to TB347 for details on reel specifications.
3. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-
020.
4.
For Moisture Sensitivity Level (MSL), please see device information page for
EL1881.
For more information on MSL, please see Technical Brief
TB363.
PART MARKING
EL1881CN
1881CS
1881CS
1881CSZ
1881CSZ
1881CSZ
8 Ld PDIP
8 Ld SOIC
8 Ld SOIC (Tape & Reel)
8 Ld SOIC (Pb-free)
8 Ld SOIC (Pb-free, Tape & Reel)
8 Ld SOIC (Pb-free, Tape & Reel)
PACKAGE
E8.3
M8.15E
M8.15E
M8.15E
M8.15E
M8.15E
PKG. DWG. #
FN7018 Rev 2.00
September 15, 2011
Page 2 of 13
EL1881
Absolute Maximum Ratings
(T
A
= +25°C)
V
CC
Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7V
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pin Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to V
CC
+0.5V
Thermal Information
Thermal Resistance (Typical, Note 5)
JA
(°C/W)
8 Lead PDIP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
85
8 Lead SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
95 to 120
Operating Ambient Temperature Range . . . . . . . . . .-40°C to +85°C
Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .400mW
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTE:
5.
JA
is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief
TB379
for details.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests
are at the specified temperature and are pulsed tests, therefore: T
J
= T
C
= T
A
DC Electrical Specifications
PARAMETER
I
DD
, Quiescent
Clamp Voltage
Clamp Discharge Current
Clamp Charge Current
R
SET
Pin Reference Voltage
V
OL
Output Low Voltage
V
OH
Output High Voltage
V
DD
= 5V, T
A
= +25°C, R
SET
= 681k, unless otherwise specified.
DESCRIPTION
V
DD
= 5V
Pin 2, I
LOAD
= -100µA
Pin 2 = 2V
Pin 2 = 1V
Pin 6
I
OL
= 1.6mA
I
OH
= -40µA
I
OH
= -1.6mA
4
3
MIN
0.75
1.35
6
-1.3
1.1
TYP
1.5
1.5
12
-1
1.22
0.24
4.8
4.6
MAX
3
1.65
16
0.7
1.35
0.5
UNIT
mA
V
µA
mA
V
V
V
V
Dynamic Specifications
PARAMETER
Comp Sync Prop Delay, t
CS
Vertical Sync Width, t
VS
Vertical Sync Default Delay, t
VSD
Burst/Back Porch Delay, t
BD
Burst/Back Porch Width, t
B
Input Dynamic Range
Slice Level
See Figure 20
Normal or Default Trigger, 50% to 50%
See Figure 21
See Figure 20
See Figure 20
Video Input Amplitude to Maintain 50% Slice Spec
V
SLICE
/V
CLAMP
DESCRIPTION
MIN
20
190
35
120
2.5
0.5
55
70
TYP
35
230
62
200
3.5
MAX
75
300
85
300
4.5
2
85
UNIT
ns
µs
µs
ns
µs
V
P-P
mV
FN7018 Rev 2.00
September 15, 2011
Page 3 of 13
EL1881
Typical Performance Curves
1.65
1.60
1.55
1.50
1.45
1.40
1.35
-50
4.5V
5.5V
5V
V
CLAMP
(V)
R
SET
= 681k
1.535
5.5V
1.525
1.515
1.505
1.495
1.485
-50
4.5V
5V
R
SET
= 681k
SUPPLY CURRENT (mA)
-25
0
25
50
75
100
-25
0
25
50
75
100
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 1. SUPPLY CURRENT vs TEMPERATURE
FIGURE 2. V
CLAMP
VOLTAGE vs TEMPERATURE
CLAMP DISCHARGE CURRENT (µA)
11.4
11.3
11.2
11.1
11.0
10.9
10.8
10.7
-50
4.5V
5.5V
R
SET
= 681k
1.240
1.235
1.230
V
RSET
(V)
5.5V
R
SET
= 681k
5V
4.5V
5V
1.225
1.220
1.215
1.210
1.205
-25
0
25
50
75
100
1.200
-50
-25
0
25
50
75
100
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 3. CLAMP DISCHARGE CURRENT vs
TEMPERATURE
FIGURE 4. V
RSET
vs TEMPERATURE
1.10
CLAMP CHARGE CURRENT (mA)
1.05
1.00
5V
0.95
0.90
0.85
-50
4.5V
R
SET
= 681k
5.5V
R
SET
(k)
1000
800
600
400
200
0
10
-25
0
25
50
75
100
15
20
25
30
35
40
45
TEMPERATURE (°C)
FREQUENCY (kHz)
FIGURE 5. CLAMP CHARGE CURRENT vs TEMPERATURE
FIGURE 6. R
SET
vs HORIZONTAL FREQUENCY
FN7018 Rev 2.00
September 15, 2011
Page 4 of 13
EL1881
Typical Performance Curves
(Continued)
6
5
BURST WIDTH (µs)
4
3
2
1
200
BURST/BACK PORCH DELAY (ns)
V
DD
= 5V, T
A
= +25°C
350
300
250
200
150
100
50
0
200
V
DD
= 5V, T
A
= +25°C
400
600
R
SET
(k)
800
1000
400
600
R
SET
(k)
800
1000
FIGURE 7. BURST/BACK PORCH WIDTH vs R
SET
FIGURE 8. BURST/BACK PORCH DELAY vs R
SET
V
DD
= 5V, T
A
= +25°C
VERTICAL SYNC DEFAULT DELAY (µs)
350
VERTICAL SYNC WIDTH (µs)
300
250
200
150
100
50
0
200
120
100
80
60
40
20
V
DD
= 5V, T
A
= +25°C
400
600
R
SET
(k)
800
1000
0
200
400
600
R
SET
(k)
800
1000
FIGURE 9. VERTICAL SYNC WIDTH vs R
SET
FIGURE 10. VERTICAL DEFAULT DELAY vs R
SET
COMPOSITE SYNC PROP DELAY (ns)
41
BURST/BACK PORCH WIDTH (µS)
39
37
35
33
31
-50
3.9
3.8
3.7
3.6
3.5
3.4
3.3
3.2
3.1
-50
-25
0
25
50
75
100
5V
4.5V
5.5V
-25
0
25
50
75
100
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 11. COMPOSITE SYNC PROP DELAY vs
TEMPERATURE
FIGURE 12. BURST/BACK PORCH WIDTH vs TEMPERATURE
FN7018 Rev 2.00
September 15, 2011
Page 5 of 13
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