HUFA76445P3, HUFA76445S3S
Data Sheet
November 2000
File Number
4987
75A, 60V, 0.0075 Ohm, N-Channel, Logic
Level UltraFET® Power MOSFET
Packaging
JEDEC TO-220AB
SOURCE
DRAIN
GATE
JEDEC TO-263AB
DRAIN
(FLANGE)
Features
• Ultra Low On-Resistance
- r
DS(ON)
= 0.0065
Ω,
V
GS
=
10V
- r
DS(ON)
= 0.0075
Ω,
V
GS
=
5V
• Simulation Models
- Temperature Compensated PSPICE® and SABER™
Electrical Models
- Spice and SABER Thermal Impedance Models
- www.Intersil.com
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
• Switching Time vs R
GS
Curves
GATE
SOURCE
DRAIN
(FLANGE)
HUFA76445P3
HUFA76445S3S
Symbol
D
Ordering Information
PART NUMBER
PACKAGE
TO-220AB
TO-263AB
BRAND
76445P
76445S
HUFA76445P3
G
S
HUFA76445S3S
NOTE: When ordering, use the entire part number. Add the suffix T
to obtain the variant in tape and reel, e.g., HUFA76445S3ST.
Absolute Maximum Ratings
T
C
= 25
o
C, Unless Otherwise Specified
HUFA76445P3, HUFA76445S3S
60
60
±
16
75
75
75
75
Figure 4
Figures 6, 17, 18
310
2.08
-55 to 175
300
260
UNITS
V
V
V
A
A
A
A
Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V
DSS
Drain to Gate Voltage (R
GS
= 20k
Ω
) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
DGR
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V
GS
Drain Current
Continuous (T
C
= 25
o
C, V
GS
= 5V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
D
Continuous (T
C
= 25
o
C, V
GS
= 10V) (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
D
Continuous (T
C
= 100
o
C, V
GS
= 5V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
D
Continuous (T
C
= 100
o
C, V
GS
= 4.5V) (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
D
Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
DM
Pulsed Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UIS
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P
D
Derate Above 25
o
C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
J
, T
STG
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
L
Package Body for 10s, See Techbrief TB334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
pkg
NOTES:
1. T
J
= 25
o
C to 150
o
C.
W
W/
o
C
o
C
o
C
o
C
CAUTION:
Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
This product has been designed to meet the extreme test conditions and environment demanded by the automotive industry. For a copy
of the requirements, see AEC Q101 at: http://www.aecouncil.com/
Reliability data can be found at: http://www.mtp.intersil.com/automotive.html.
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 and QS9000 quality systems certification.
©2001 Fairchild Semiconductor Corporation
HUFA76445P3, HUFA76445S3S Rev. A
HUFA76445P3, HUFA76445S3S
Electrical Specifications
PARAMETER
OFF STATE SPECIFICATIONS
Drain to Source Breakdown Voltage
BV
DSS
I
DSS
I
GSS
V
GS(TH)
r
DS(ON)
I
D
= 250
µ
A, V
GS
= 0V (Figure 12)
I
D
= 250
µ
A, V
GS
= 0V , T
C
= -40
o
C (Figure 12)
Zero Gate Voltage Drain Current
V
DS
= 55V, V
GS
= 0V
V
DS
= 50V, V
GS
= 0V, T
C
= 150
o
C
Gate to Source Leakage Current
ON STATE SPECIFICATIONS
Gate to Source Threshold Voltage
Drain to Source On Resistance
V
GS
= V
DS
, I
D
= 250
µ
A (Figure 11)
I
D
= 75A, V
GS
= 10V (Figures 9, 10)
I
D
= 75A, V
GS
= 5V (Figure 9)
I
D
= 75A, V
GS
= 4.5V (Figure 9)
THERMAL SPECIFICATIONS
Thermal Resistance Junction to Case
Thermal Resistance Junction to
Ambient
R
θ
JC
R
θ
JA
TO-220 and TO-263
-
-
-
-
0.48
62
o
C/W
o
C/W
T
C
= 25
o
C, Unless Otherwise Specified
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
60
55
-
-
-
-
-
-
-
-
-
-
1
250
±
100
3
0.0065
0.0075
0.008
V
V
µ
A
µ
A
nA
V
GS
=
±
16V
1
-
-
-
-
0.0054
0.0063
0.0066
V
Ω
Ω
Ω
SWITCHING SPECIFICATIONS
(V
GS
= 4.5V)
Turn-On Time
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Turn-Off Time
t
ON
t
d(ON)
t
r
t
d(OFF)
t
f
t
OFF
t
ON
t
d(ON)
t
r
t
d(OFF)
t
f
t
OFF
Q
g(TOT)
Q
g(5)
Q
g(TH)
Q
gs
Q
gd
C
ISS
C
OSS
C
RSS
V
DS
= 25V, V
GS
= 0V,
f = 1MHz
(Figure 13)
V
GS
= 0V to 10V
V
GS
= 0V to 5V
V
GS
= 0V to 1V
V
DD
= 30V,
I
D
= 75A,
I
g(REF)
= 1.0mA
(Figures 14, 19, 20)
V
DD
= 30V, I
D
= 75A
V
GS
=
10V,
R
GS
= 2.4
Ω
(Figures 16, 21, 22)
V
DD
= 30V, I
D
= 75A
V
GS
=
4.5V, R
GS
= 2.2
Ω
(Figures 15, 21, 22)
-
-
-
-
-
-
-
18
325
39
135
-
515
-
-
-
-
260
ns
ns
ns
ns
ns
ns
SWITCHING SPECIFICATIONS
(V
GS
= 10V)
Turn-On Time
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Turn-Off Time
GATE CHARGE SPECIFICATIONS
Total Gate Charge
Gate Charge at 5V
Threshold Gate Charge
Gate to Source Gate Charge
Gate to Drain “Miller” Charge
CAPACITANCE SPECIFICATIONS
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
-
-
-
4965
1250
150
-
-
-
pF
pF
pF
-
-
-
-
-
124
68
5
14
30
150
81
6
-
-
nC
nC
nC
nC
nC
-
-
-
-
-
-
-
12
126
62
135
-
205
-
-
-
-
295
ns
ns
ns
ns
ns
ns
Source to Drain Diode Specifications
PARAMETER
Source to Drain Diode Voltage
SYMBOL
V
SD
t
rr
Q
RR
I
SD
= 75A
I
SD
= 35A
Reverse Recovery Time
Reverse Recovered Charge
I
SD
= 75A, dI
SD
/dt = 100A/µs
I
SD
= 75A, dI
SD
/dt = 100A/µs
TEST CONDITIONS
MIN
-
-
-
-
TYP
-
-
-
-
MAX
1.25
1.00
100
260
UNITS
V
V
ns
nC
©2001 Fairchild Semiconductor Corporation
HUFA76445P3, HUFA76445S3S Rev. A
HUFA76445P3, HUFA76445S3S
Typical Performance Curves
1.2
POWER DISSIPATION MULTIPLIER
1.0
0.8
0.6
0.4
0.2
0
0
25
50
75
100
125
150
175
T
C
, CASE TEMPERATURE (
o
C)
0
25
50
75
100
125
150
T
C
, CASE TEMPERATURE (
o
C)
80
V
GS
= 10V
60
V
GS
= 4.5V
40
I
D
, DRAIN CURRENT (A)
20
175
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE
TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPERATURE
2
1
THERMAL IMPEDANCE
Z
θJC
, NORMALIZED
DUTY CYCLE - DESCENDING ORDER
0.5
0.2
0.1
0.05
0.02
0.01
P
DM
0.1
t
1
t
2
SINGLE PULSE
0.01
10
-5
10
-4
10
-3
10
-2
t, RECTANGULAR PULSE DURATION (s)
10
-1
NOTES:
DUTY FACTOR: D = t
1
/t
2
PEAK T
J
= P
DM
x Z
θJC
x R
θJC
+ T
C
10
0
10
1
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
2000
T
C
= 25
o
C
FOR TEMPERATURES
ABOVE 25
o
C DERATE PEAK
CURRENT AS FOLLOWS:
I = I
25
V
GS
= 10V
V
GS
= 5V
175 - T
C
150
I
DM
, PEAK CURRENT (A)
1000
100
50
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
10
-4
10
-3
10
-2
t, PULSE WIDTH (s)
10
-1
10
0
10
1
10
-5
FIGURE 4. PEAK CURRENT CAPABILITY
©2001 Fairchild Semiconductor Corporation
HUFA76445P3, HUFA76445S3S Rev. A
HUFA76445P3, HUFA76445S3S
Typical Performance Curves
1000
(Continued)
1000
I
AS
, AVALANCHE CURRENT (A)
If R = 0
t
AV
= (L)(I
AS
)/(1.3*RATED BV
DSS
- V
DD
)
If R
≠
0
t
AV
= (L/R)ln[(I
AS
*R)/(1.3*RATED BV
DSS
- V
DD
) +1]
I
D
, DRAIN CURRENT (A)
100
100µs
100
STARTING T
J
= 25
o
C
1ms
10
OPERATION IN THIS
AREA MAY BE
LIMITED BY r
DS(ON)
SINGLE PULSE
T
J
= MAX RATED
T
C
= 25
o
C
1
10
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
100
10ms
STARTING T
J
= 150
o
C
1
10
0.01
0.1
1
10
t
AV
, TIME IN AVALANCHE (ms)
NOTE: Refer to Intersil Application Notes AN9321 and AN9322.
FIGURE 5. FORWARD BIAS SAFE OPERATING AREA
FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING
CAPABILITY
150
I
D,
DRAIN CURRENT (A)
I
D
, DRAIN CURRENT (A)
120
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
V
DD
= 15V
150
V
GS
= 10V
V
GS
= 5V
V
GS
= 4V
V
GS
= 3.5V
120
90
90
60
T
J
= 175
o
C
30
T
J
= 25
o
C
T
J
= -55
o
C
1.5
2
2.5
3
3.5
V
GS
, GATE TO SOURCE VOLTAGE (V)
4
60
V
GS
= 3V
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
T
C
= 25
o
C
0
1
2
3
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
4
30
0
0
FIGURE 7. TRANSFER CHARACTERISTICS
FIGURE 8. SATURATION CHARACTERISTICS
25
NORMALIZED DRAIN TO SOURCE
ON RESISTANCE
I
D
= 75A
r
DS(ON)
, DRAIN TO SOURCE
ON RESISTANCE (mΩ)
20
I
D
= 35A
15
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
T
C
= 25
o
C
2.5
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
2.0
V
GS
= 10V, I
D
= 75A
1.5
10
I
D
= 20A
5
2
4
6
8
V
GS
, GATE TO SOURCE VOLTAGE (V)
10
1.0
0.5
-80
-40
0
40
80
120
T
J
, JUNCTION TEMPERATURE (
o
C)
160
200
FIGURE 9. DRAIN TO SOURCE ON RESISTANCE vs GATE
VOLTAGE AND DRAIN CURRENT
FIGURE 10. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
©2001 Fairchild Semiconductor Corporation
HUFA76445P3, HUFA76445S3S Rev. A
HUFA76445P3, HUFA76445S3S
Typical Performance Curves
1.2
NORMALIZED DRAIN TO SOURCE
BREAKDOWN VOLTAGE
V
GS
= V
DS
, I
D
= 250µA
NORMALIZED GATE
THRESHOLD VOLTAGE
(Continued)
1.2
I
D
= 250µA
1.0
1.1
0.8
1.0
0.6
0.4
-80
-40
0
40
80
120
160
200
T
J
, JUNCTION TEMPERATURE (
o
C)
0.9
-80
-40
0
40
80
120
160
200
T
J
, JUNCTION TEMPERATURE (
o
C)
FIGURE 11. NORMALIZED GATE THRESHOLD VOLTAGE vs
JUNCTION TEMPERATURE
FIGURE 12. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
10
V
GS
, GATE TO SOURCE VOLTAGE (V)
10000
C
ISS
=
C
GS
+ C
GD
V
DD
= 30V
8
C, CAPACITANCE (pF)
C
RSS
=
C
GD
1000
C
OSS
≅
C
DS
+ C
GD
6
4
WAVEFORMS IN
DESCENDING ORDER:
I
D
= 75A
I
D
= 35A
0
30
60
90
120
150
2
V
GS
= 0V, f = 1MHz
100
0.1
1.0
10
60
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
0
Q
g
, GATE CHARGE (nC)
NOTE: Refer to Intersil Application Notes AN7254 and AN7260.
FIGURE 13. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
FIGURE 14. GATE CHARGE WAVEFORMS FOR CONSTANT
GATE CURRENT
1200
V
GS
= 4.5V, V
DD
= 30V, I
D
= 75A
1000
SWITCHING TIME (ns)
SWITCHING TIME (ns)
t
r
800
800
V
GS
= 10V, V
DD
= 30V, I
D
= 75A
t
d(OFF)
600
t
f
400
t
r
200
t
d(ON)
0
0
10
20
30
40
R
GS
, GATE TO SOURCE RESISTANCE (Ω)
50
0
10
20
30
40
R
GS
, GATE TO SOURCE RESISTANCE (Ω)
50
600
t
f
400
t
d(OFF)
200
t
d(ON)
0
FIGURE 15. SWITCHING TIME vs GATE RESISTANCE
FIGURE 16. SWITCHING TIME vs GATE RESISTANCE
©2001 Fairchild Semiconductor Corporation
HUFA76445P3, HUFA76445S3S Rev. A
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