HUFA75309T3ST
Data Sheet
December 2001
3A, 55V, 0.070 Ohm, N-Channel UltraFET
Power MOSFET
This N-Channel power MOSFET is
manufactured using the innovative
UltraFET® process. This advanced
process technology achieves the
lowest possible on-resistance per silicon area, resulting in
outstanding performance. This device is capable of
withstanding high energy in the avalanche mode and the
diode exhibits very low reverse recovery time and stored
charge. It was designed for use in applications where power
efficiency is important, such as switching regulators,
switching converters, motor drivers, relay drivers, low-
voltage bus switches, and power management in portable
and battery operated products.
Formerly developmental type TA75309.
Features
• 3A, 55V
• Ultra Low On-Resistance, r
DS(ON)
= 0.070Ω
• Diode Exhibits Both High Speed and Soft Recovery
• Temperature Compensating PSPICE
®
Model
• Thermal Impedance SPICE Model
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
• Related Literature
- TB334, “Guidelines for Soldering Surface Mount
Components to PC Boards”
Symbol
D
Ordering Information
PART NUMBER
HUFA75309T3ST
PACKAGE
SOT-223
5309
S
BRAND
G
NOTE: HUFA75309T3ST is available only in tape and reel.
Packaging
SOT-223
DRAIN
(FLANGE)
GATE
DRAIN
SOURCE
This product has been designed to meet the extreme test conditions and environment demanded by the automotive industry. For a copy
of the requirements, see AEC Q101 at: http://www.aecouncil.com/
Reliability data can be found at: http://www.fairchildsemi.com/products/discrete/reliability/index.html.
All Fairchild semiconductor products are manufactured, assembled and tested under ISO9000 and QS9000 quality systems certification.
©2001 Fairchild Semiconductor Corporation
HUFA75309T3ST Rev. B
HUFA75309T3ST
Absolute Maximum Ratings
T
A
= 25
o
C, Unless Otherwise Specified
HUFA75309T3ST
55
55
±20V
3
Figure 5
Figures 6, 14, 15
1.1
9.09
-55 to 150
300
260
UNITS
V
V
V
A
Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
DSS
Drain to Gate Voltage (R
GS
= 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
DGR
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
GS
Drain Current
Continuous (Note 2) (Figure 2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
D
Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
DM
Pulsed Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E
AS
Power Dissipation (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P
D
Derate Above 25
o
C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
J
, T
STG
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
L
Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
pkg
W
mW/
o
C
o
C
o
C
o
C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. T
J
= 25
o
C to 125
o
C.
Electrical Specifications
PARAMETER
T
A
= 25
o
C, Unless Otherwise Specified
SYMBOL
BV
DSS
V
GS(TH)
I
DSS
I
GSS
r
DS(ON)
t
ON
t
d(ON)
t
r
t
d(OFF)
t
f
t
OFF
Q
g(TOT)
Q
g(10)
Q
g(TH)
Q
gs
Q
gd
C
ISS
C
OSS
C
RSS
R
θJA
Pad Area = 0.164 in
2
(See note 2)
Pad Area = 0.068 in
2
(See TB377)
Pad Area = 0.026 in
2
(See TB377)
V
DS
= 25V, V
GS
= 0V, f = 1MHz
(Figure 12)
V
GS
= 0V to 20V
V
GS
= 0V to 10V
V
GS
= 0V to 2V
V
DD
= 30V, I
D
≅
3A,
R
L
= 10Ω
I
g(REF)
= 1.0mA
(Figure 13)
TEST CONDITIONS
I
D
= 250µA, V
GS
= 0V (Figure 11)
V
GS
= V
DS
, I
D
= 250µA (Figure 10)
V
DS
= 50V, V
GS
= 0V
V
DS
= 45V, V
GS
= 0V, T
A
= 150
o
C
V
GS
=
±20V
I
D
= 3A, V
GS
= 10V (Figure 9)
V
DD
= 30V, I
D
≅
3A, R
L
= 10Ω,
V
GS
=
10V, R
GS
= 28Ω
MIN
55
2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
TYP
-
-
-
-
-
0.057
-
8
20
12
28
-
19
10.7
0.71
1.40
4.80
352
146
30
-
-
-
MAX
-
4
1
250
100
0.070
45
-
-
-
-
65
23
13
0.85
-
-
-
-
-
110
126
143
UNITS
V
V
µA
µA
nA
Ω
ns
ns
ns
ns
ns
ns
nC
nC
nC
nC
nC
pF
pF
pF
o
C/W
o
C/W
o
C/W
Drain to Source Breakdown Voltage
Gate to Source Threshold Voltage
Zero Gate Voltage Drain Current
Gate to Source Leakage Current
Drain to Source On Resistance
Turn-On Time
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Turn-Off Time
Total Gate Charge
Gate Charge at 10V
Threshold Gate Charge
Gate to Source Gate Charge
Gate to Drain “Miller” Charge
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Thermal Resistance Junction to Ambient
Source to Drain Diode Specifications
PARAMETER
Source to Drain Diode Voltage
Reverse Recovery Time
Reverse Recovered Charge
NOTE:
2. 110
o
C/W measured using FR-4 board with 0.164 in
2
footprint for 1000 seconds.
©2001 Fairchild Semiconductor Corporation
HUFA75309T3ST Rev. B
SYMBOL
V
SD
t
rr
Q
RR
I
SD
= 3A
TEST CONDITIONS
MIN
-
-
-
TYP
-
-
-
MAX
1.25
41
59
UNITS
V
ns
nC
I
SD
= 3A, dI
SD
/dt = 100A/µs
I
SD
= 3A, dI
SD
/dt = 100A/µs
HUFA75309T3ST
Typical Performance Curves
4
R
θJA
= 110
o
C/W
I
D
, DRAIN CURRENT (A)
0
25
50
75
100
125
150
3
1.2
POWER DISSIPATION MULTIPLIER
1.0
0.8
0.6
0.4
0.2
0
T
A
, AMBIENT TEMPERATURE (
o
C)
2
1
0
25
50
75
100
125
150
T
A
, AMBIENT TEMPERATURE (
o
C)
FIGURE 1. NORMALIZED POWER DISSIPATION vs AMBIENT
TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
AMBIENT TEMPERATURE
1
Z
θ
JA
, NORMALIZED
THERMAL IMPEDANCE
0.1
DUTY CYCLE - DESCENDING ORDER
0.5
0.2
0.1
0.05
0.02
0.01
P
DM
0.01
t
1
t
2
NOTES:
DUTY FACTOR: D = t
1
/t
2
PEAK T
J
= P
DM
x Z
θ
JA
x R
θ
JA
+ T
A
10
-2
10
-1
10
0
10
1
10
2
10
3
SINGLE PULSE
0.001
10
-5
10
-4
10
-3
t, RECTANGULAR PULSE DURATION (s)
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
100
T
J
= MAX RATED
T
A
= 25
o
C
R
θJA
= 110
o
C/W
10
100µs
1ms
1
10ms
OPERATION IN THIS
AREA MAY BE
LIMITED BY r
DS(ON)
1
50
FOR TEMPERATURES
T
A
= 25
o
C
o
o
C/W ABOVE 25 C DERATE PEAK
R
θJA
= 110
CURRENT AS FOLLOWS:
I = I
25
150 - T
A
125
I
D
, DRAIN CURRENT (A)
I
DM
, PEAK CURRENT (A)
10
0.1
V
DSS
(
MAX
) = 55V
1
200
10
-3
10
-2
10
-1
10
0
10
1
t, PULSE WIDTH (s)
10
2
10
3
10
100
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
FIGURE 4. FORWARD BIAS SAFE OPERATING AREA
FIGURE 5. PEAK CURRENT CAPABILITY
©2001 Fairchild Semiconductor Corporation
HUFA75309T3ST Rev. B
HUFA75309T3ST
Typical Performance Curves
20
I
AS
, AVALANCHE CURRENT (A)
(Continued)
25
V
GS
= 20V
V
GS
= 10V
I
D
, DRAIN CURRENT (A)
20
V
GS
= 8V
15
V
GS
= 7V
V
GS
= 6V
V
GS
= 5V
5
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
T
A
= 25
o
C
0
1
2
3
4
5
If R = 0
t
AV
= (L)(I
AS
)/(1.3*RATED BV
DSS
- V
DD
)
If R
≠
0
t
AV
= (L/R)ln[(I
AS
*R)/(1.3*RATED BV
DSS
- V
DD
) +1]
10
STARTING T
J
= 25
o
C
10
STARTING T
J
= 150
o
C
1
0.01
0
0.1
1
10
100
t
AV
, TIME IN AVALANCHE (ms)
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
NOTE: Refer to Fairchild Application Notes AN9321 and AN9322.
FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING CAPABILITY
25
2.0
NORMALIZED DRAIN TO SOURCE
ON RESISTANCE
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
V
DD
= 15V
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
V
GS
= 10V, I
D
= 3A
1.5
FIGURE 7. SATURATION CHARACTERISTICS
I
D,
DRAIN CURRENT (A)
20
15
10
25
o
C
5
150
o
C
-55
o
C
0
0
1.5
3.0
4.5
6.0
V
GS
, GATE TO SOURCE VOLTAGE (V)
7.5
1.0
0.5
-80
-40
0
40
80
120
160
T
J
, JUNCTION TEMPERATURE (
o
C)
FIGURE 8. TRANSFER CHARACTERISTICS
FIGURE 9. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
1.2
NORMALIZED DRAIN TO SOURCE
BREAKDOWN VOLTAGE
1.2
V
GS
= V
DS
, I
D
= 250µA
NORMALIZED GATE
THRESHOLD VOLTAGE
I
D
= 250µA
1.1
1.0
0.8
1.0
0.6
0.9
0.4
-80
-40
0
40
80
120
160
T
J
, JUNCTION TEMPERATURE (
o
C)
0.8
-80
-40
0
40
80
120
160
T
J
, JUNCTION TEMPERATURE (
o
C)
FIGURE 10. NORMALIZED GATE THRESHOLD VOLTAGE vs
JUNCTION TEMPERATURE
FIGURE 11. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
©2001 Fairchild Semiconductor Corporation
HUFA75309T3ST Rev. B
HUFA75309T3ST
Typical Performance Curves
600
500
C, CAPACITANCE (pF)
400
C
ISS
300
200
100
0
0
10
20
30
40
50
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
60
V
GS
= 0V, f = 1MHz
C
ISS
= C
GS
+ C
GD
C
RSS
= C
GD
C
OSS
= C
DS
+ C
GD
(Continued)
10
V
GS
, GATE TO SOURCE VOLTAGE (V)
8
WAVEFORMS IN
DESCENDING ORDER:
I
D
= 3A
I
D
= 1A
V
DD
= 30V
6
4
C
OSS
C
RSS
2
0
0
2
4
6
8
Q
g
, GATE CHARGE (nC)
10
12
FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
NOTE: Refer to Fairchild Application Notes AN7254 and AN7260.
FIGURE 13. GATE CHARGE WAVEFORMS FOR CONSTANT
GATE CURRENT
Test Circuits and Waveforms
V
DS
t
P
L
VARY t
P
TO OBTAIN
REQUIRED PEAK I
AS
V
GS
DUT
t
P
0
I
AS
0.01Ω
t
AV
R
G
-
I
AS
+
BV
DSS
V
DS
V
DD
V
DD
0V
FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 15. UNCLAMPED ENERGY WAVEFORMS
V
DS
R
L
V
DD
V
DS
V
GS
= 20V
V
GS
+
Q
g(TOT)
Q
g(10)
V
DD
V
GS
V
GS
= 2V
0
Q
g(TH)
I
g(REF)
0
V
GS
= 10V
-
DUT
I
g(REF)
FIGURE 16. GATE CHARGE TEST CIRCUIT
FIGURE 17. GATE CHARGE WAVEFORM
©2001 Fairchild Semiconductor Corporation
HUFA75309T3ST Rev. B
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