LTC1346A
10Mbps DCE/DTE
V.35 Transceiver
FEATURES
s
s
DESCRIPTIO
s
s
s
s
s
s
s
s
Single Chip Provides Complete Differential Signal
Interface for V.35 Port
Drivers and Receivers Will Withstand Repeated
±10kV
ESD Pulses
10Mbaud Transmission Rate
Meets CCITT V.35 Specification
Operates from
±5V
Supplies
Shutdown Mode Reduces I
CC
to Below 1µA
Selectable Transmitter and Receiver Configurations
Independent Driver/Receiver Enables
Transmitter Maintains High Impedance When
Disabled, Shut Down or with Power Off
Transmitters Are Short-Circuit Protected
The LTC
®
1346A is a single chip transceiver that provides
the differential clock and data signals for a V.35 interface
from
±5V
supplies. Combined with an external resistor
termination network and an LT
®
1134A RS232 transceiver
for the control signals, the LTC1346A forms a complete low
power DTE or DCE V.35 interface port.
The LTC1346A features three current output differential
transmitters and three differential receivers. The trans-
ceiver can be configured for DTE or DCE operation or
shutdown using three Select pins. In the shutdown mode,
the supply current is reduced to below 1µA.
The LTC1346A transceiver operates up to 10Mbaud. All
transmitters feature short-circuit protection. Both the trans-
mitter outputs and the receiver outputs can be forced into
a high impedance state. The transmitter outputs and re-
ceiver inputs feature
±10kV
ESD protection.
, LTC and LT are registered trademarks of Linear Technology Corporation.
APPLICATI
s
s
s
S
Modems
Telecommunications
Data Routers
TYPICAL APPLICATION
Clock and Data Signals for V.35 Interface
V
EE1
– 5V
+
0.1µF
1
V
CC1
5V
2
0.1µF
4
LTC1346A
24
DX
23
22
5
DX
21
1
2
3
4
T
TXC (114)
T
RXC (115)
T
RXD (104)
T
GND (102)
T
T
T
T
SCTE (113)
T
BI
627T500/1250
TXD (103)
T
BI
627T500/1250
12
11
10
9
1
2
3
4
5
6
7
16
15
14
13
24
23
22
21
20
19
3
12
DX
6
7
8
V
CC2
T
=
50Ω
BI TECHNOLOGIES
627T500/1250 (SOIC)
LTC1346 • TA01
DTE
DCE
LTC1346A
+
0.1µF
10
RX
RX
11
18 14
9
RX
17 13
16 12
10
RX
15 11
14 10
11
7
V
CC1
8
12
RX
13
3
9
8
DX
4
DX
5
50Ω
7
8
+
U
1
2
V
CC2
5V
V
EE2
–5V
0.1µF
125Ω
U
UO
+
1
LTC1346A
ABSOLUTE
(Note 1)
AXI U
RATI GS
PACKAGE/ORDER I FOR ATIO
TOP VIEW
V
EE
1
V
CC
2
GND 3
T1 4
T2 5
T3 6
S1 7
S2 8
R3 9
R2 10
R1 11
S0 12
24 Y1
23 Z1
22 Y2
21 Z2
20 Y3
19 Z3
18 A3
17 B3
16 A2
15 B2
14 A1
13 B1
Supply Voltage
V
CC
.................................................................... 6.5V
V
EE
................................................................... – 6.5V
Input Voltage
Transmitters ........................... – 0.3V to (V
CC
+ 0.3V)
Receivers ............................................... – 18V to 18V
S0, S1, S2 ............................... – 0.3V to (V
CC
+ 0.3V)
Output Voltage
Transmitters .......................................... – 18V to 18V
Receivers ................................ – 0.3V to (V
CC
+ 0.3V)
Short-Circuit Duration
Transmitter Output ..................................... Indefinite
Receiver Output .......................................... Indefinite
Operating Temperature Range
LTC1346AC ............................................ 0°C to 70°C
LTC1346AI ........................................ – 40°C to 85°C
Storage Temperature Range ................ – 65°C to 150°C
Lead Temperature (Soldering, 10 sec)................. 300°C
ORDER PART
NUMBER
LTC1346ACSW
LTC1346AISW
SW PACKAGE
24-LEAD PLASTIC SO WIDE
T
JMAX
= 150°C,
θ
JA
= 85°C/W
Consult factory for Military grade parts.
DC ELECTRICAL CHARACTERISTICS
SYMBOL
V
OD
V
OC
I
OH
I
OL
I
OZ
R
O
V
TH
∆V
TH
I
IN
R
IN
V
OH
V
OL
I
OSR
I
OZR
V
IH
V
IL
I
IN
PARAMETER
Transmitter Differential Output Voltage
Transmitter Common Mode Output Voltage
Transmitter Output High Current
Transmitter Output Low Current
Transmitter Output Leakage Current
Transmitter Output Impedance
Differential Receiver Input Threshold Voltage
Receiver Input Hysterisis
Receiver Input Current (A, B)
Receiver Input Impedance
Receiver Output High Voltage
Receiver Output Low Voltage
Receiver Output Short-Circuit Current
Receiver Three-State Output Current
Logic Input High Voltage
Logic Input Low Voltage
Logic Input Current
V
CC
= 5V
±5%,
V
EE
= – 5V
±5%
(Note 2)
q
q
q
q
q
CONDITIONS
– 4V
≤
V
OS
≤
4V (Figure 1)
V
OS
= 0V (Figure 1)
V
Y, Z
= 0V
V
Y, Z
= 0V
– 5V
≤
V
Y, Z
≤
5V, S1 = S2 = 0V
– 2V
≤
V
Y, Z
≤
2V
– 7V
≤
(V
A
+ V
B
)/2
≤
12V
– 7V
≤
(V
A
+ V
B
)/2
≤
12V
– 7V
≤
V
A, B
≤
12V
– 7V
≤
V
A, B
≤
12V
I
O
= 4mA, V
A, B
= 0.2V
I
O
= 4mA, V
A, B
= – 0.2V
0V
≤
V
O
≤
V
CC
S0 = V
CC
, 0V
≤
V
O
≤
V
CC
T, S0, S1, S2
T, S0, S1, S2
T, S0, S1, S2
MIN
0.44
– 0.6
– 12.6
9.4
TYP
0.55
0
– 11
11
±1
100
25
50
MAX
0.66
0.6
– 9.4
12.6
±20
±100
200
0.7
q
q
q
q
q
q
q
q
q
q
17.5
3
7
2
30
4.5
0.2
40
0.4
85
±10
0.8
±10
UNITS
V
V
mA
mA
µA
µA
kΩ
mV
mV
mA
kΩ
V
V
mA
µA
V
V
µA
2
U
W
U
U
W W
W
LTC1346A
AC ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER
I
CC
V
CC
Supply Current
V
CC
= 5V
±5%,
V
EE
= – 5V
±5%
(Note 2)
MIN
q
q
q
q
q
q
q
q
q
q
q
q
I
EE
V
EE
Supply Current
t
r
, t
f
t
PLH
t
PHL
t
SKEW
t
PLH
t
PHL
t
SKEW
t
ZL
t
ZH
t
LZ
t
HZ
Transmitter Rise or Fall Time
Transmitter Input to Output
Transmitter Input to Output
Transmitter Output to Output
Receiver Input to Output
Receiver Input to Output
Differential Receiver Skew,
t
PLH
– t
PHL
Receiver Enable to Output Low (Active Mode)
Receiver Enable to Output Low
(from Shutdown, Note 3)
Receiver Enable to Output High (Active Mode)
Receiver Enable to Output High
(from Shutdown, Note 3)
Receiver Disable from Low
Receiver Disable from High
CONDITIONS
V
OS
= 0V, S0 = Low, S1 = S2 = High (Figure 1)
No Load, S0 = Low, S1 = S2 = High
Shutdown, S0 = V
CC
, S1 = S2 = 0V
V
OS
= 0V, S0 = Low, S1 = S2 = High (Figure 1)
No Load, S0 = Low, S1 = S2 = High
Shutdown, S0 = V
CC
, S1 = S2 = 0V
V
OS
= 0V (Figures 1, 3)
V
OS
= 0V (Figures 1, 3)
V
OS
= 0V (Figures 1, 3)
V
OS
= 0V (Figures 1, 3)
V
OS
= 0V (Figures 1, 4)
V
OS
= 0V (Figures 1, 4)
V
OS
= 0V (Figures 1, 4)
C
L
= 15pF, SW1 Closed (Figures 2, 5)
C
L
= 15pF, SW1 Closed (Figures 2, 5)
C
L
= 15pF, SW2 Closed (Figures 2, 5)
C
L
= 15pF, SW2 Closed (Figures 2, 5)
C
L
= 15pF, SW1 Closed (Figures 2, 5)
C
L
= 15pF, SW2 Closed (Figures 2, 5)
TYP
40
6
0.1
– 40
–6
– 0.1
7
25
30
5
50
55
5
40
2
35
2
30
35
MAX
50
9
100
– 50
–9
– 100
40
70
70
100
100
70
UNITS
mA
mA
µA
mA
mA
µA
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
µs
ns
ns
q
70
q
q
70
70
The
q
denotes specifications which apply over the full operating
temperature range.
Note 1:
The Absolute Maximum Ratings are those values beyond which
the life of a device may be impaired.
Note 2:
All currents into device pins are positive; all currents out of device
pins are termed negative. All voltages are referenced to device ground
unless otherwise specified.
Note 3:
Receiver enable to output valid high or low from shutdown is
typically 2µs.
TYPICAL PERFORMANCE CHARACTERISTICS
Transmitter Output Current
vs Temperature
13
V
CC
= 5V
V
EE
= –5V
OUTPUT
CURRENT (mA)
13
T
A
= 25°C
V
CC
= 5V
V
EE
= –5V
12
12
OUTPUT
CURRENT (mA)
11
TIME (ns)
10
9
–50 –25
0
50
75
25
TEMPERATURE (˚C)
U W
100
1346A G01
Transmitter Output Current
vs Output Voltage
20
Transmitter Output Skew
vs Temperature
V
CC
= 5V
V
EE
= –5V
15
11
10
10
5
125
9
–2.0 –1.5 –1.0 –0.5 0 0.5 1.0
OUTPUT VOLTAGE (V)
1.5
2.0
0
–50 –25
0
50
75
25
TEMPERATURE (˚C)
100
125
1346A G02
1346A G03
3
LTC1346A
TYPICAL PERFORMANCE CHARACTERISTICS
Receiver t
PLH
– t
PHL
vs Temperature
20
V
CC
= 5V
V
EE
= –5V
15
CURRENT (mA)
TIME (ns)
CURRENT (mA)
10
5
0
–50 –25
0
50
75
25
TEMPERATURE (˚C)
Transmitter Output Waveforms
INPUT
5V/DIV
OUTPUT
0.2V/DIV
PIN FUNCTIONS
V
EE
(Pin 1):
Negative Supply, – 4.75V
≥
V
EE
≥
– 5.25V
V
CC
(Pin 2):
Positive Supply, 4.75V
≤
V
CC
≤
5.25V
GND (Pin 3):
Ground
T1 (Pin 4):
Transmitter 1 Input, TTL Compatible
T2 (Pin 5):
Transmitter 2 Input, TTL Compatible
T3 (Pin 6):
Transmitter 3 Input, TTL Compatible
S1 (Pin 7):
Select Input 1, TTL Compatible
S2 (Pin 8):
Select Input 2, TTL Compatible
R3 (Pin 9):
Receiver 3 Output, TTL Compatible
R2 (Pin 10):
Receiver 2 Output, TTL Compatible
R1 (Pin 11):
Receiver 1 Output, TTL Compatible
S0 (Pin 12):
Select Input 0, TTL Compatible
B1 (Pin 13):
Receiver 1 Inverting Input
A1 (Pin 14):
Receiver 1 Noninverting Input
B2 (Pin 15):
Receiver 2 Inverting Input
A2 (Pin 16):
Receiver 2 Noninverting Input
B3 (Pin 17):
Receiver 3 Inverting Input
A3 (Pin 18):
Receiver 3 Noninverting Input
Z3 (Pin 19):
Transmitter 3 Inverting Output
Y3 (Pin 20):
Transmitter 3 Noninverting Output
Z2 (Pin 21):
Transmitter 2 Inverting Output
Y2 (Pin 22):
Transmitter 2 Noninverting Output
Z1 (Pin 23):
Transmitter 1 Inverting Output
Y1 (Pin 24):
Transmitter 1 Noninverting Output
4
U W
100
1346A G04
I
CC
Supply Current vs Temperature
45
LOADED
40
V
CC
= 5V
V
EE
= –5V
7.0
CURRENT (mA)
I
EE
Supply Current vs Temperature
7.5
–25
V
CC
= 5V
V
EE
= –5V
–30
NO LOAD
–35
–6.0
–5.5
CURRENT (mA)
–5.0
35
6.5
NO LOAD
30
6.0
LOADED
–40
–6.5
125
25
–50 –25
0
50
75
25
TEMPERATURE (˚C)
100
5.5
125
–45
–50 –25
0
50
75
25
TEMPERATURE (˚C)
100
–7.0
125
1346A G05
1346A G06
Receiver Output Waveforms
INPUT A–B
1V/DIV
INPUT S0
5V/DIV
OUTPUT
5V/DIV
OUTPUT
5V/DIV
Receiver Enable from Shutdown
INPUT
0.2V/DIV
1346A G07
1346A G08
1346A G09
U
U
U
LTC1346A
FU CTIO TABLES
Transmitter and Receiver Configuration
S0
0
1
0
1
0
1
0
1
S1
0
0
1
1
0
0
1
1
S2
0
0
0
0
1
1
1
1
DX ON
—
—
1, 2, 3
1, 2, 3
1, 2
1, 2
1, 2, 3
1, 2, 3
RX ON
1, 2, 3
—
1, 2
—
1, 2, 3
—
1, 2, 3
—
Description
All RX ON, All DX OFF
All OFF, Shutdown
DCE Mode
DCE Mode, All RX OFF
DTE Mode
DTE Mode, All RX OFF
All ON
All DX ON, All RX OFF
TEST CIRCUITS
Y
50Ω
T
Y
V
OD
Z
B
50Ω
V
OC
= (V
Y
+ V
Z
)/2
Z
50Ω
125Ω
50Ω
125Ω
A
R
S0
15pF
V
OS
U
U
Transmitter
INPUTS
CONFIGURATION S0 S1 S2
All OFF
Shutdown
DCE or All ON
DCE or All ON
DTE
DTE
0
1
X
X
X
X
0
0
1
1
0
0
0
0
X
X
1
1
X
X
0
1
0
1
Z
Z
0
1
0
1
OUTPUTS
T Y1 AND Y2 Z1 AND Z2 Y3 Z3
Z
Z
1
0
1
0
Z
Z
0
1
Z
Z
Z
Z
1
0
Z
Z
Receiver
INPUTS
CONFIGURATION S0 S1 S2
All Rx ON
All Rx ON
Shutdown
DCE
DCE
Disabled
DTE or All ON
DTE or All ON
Disabled
0
0
1
0
0
1
0
0
1
0
0
0
1
1
1
X
X
X
0
0
0
0
0
0
1
1
1
A–B
≤
– 0.2V
≥
0.2V
X
≤
– 0.2V
≥
0.2V
X
≤
– 0.2V
≥0.2V
X
OUTPUTS
R1 AND R2
0
1
Z
0
1
Z
0
1
Z
R3
0
1
Z
Z
Z
Z
0
1
Z
LTC1346A • F01
Figure 1. V.35 Transmitter/Receiver Test Circuit
V
CC
SW1
RECEIVER
OUTPUT
C
L
1k
SW2
LTC1346A • F02
Figure 2. Receiver Output Enable and Disable Timing Test Load
5
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
