LTC1391
8-Channel
Analog Multiplexer with
Cascadable Serial Interface
FEATURES
s
s
s
s
s
s
s
s
s
s
DESCRIPTION
The LTC
®
1391 is a high performance CMOS 8-to-1 analog
multiplexer. It features a serial digital interface that allows
several LTC1391s to be daisy-chained together, increas-
ing the number of MUX channels available using a single
digital port.
The LTC1391 features a typical R
ON
of 45Ω, a typical
switch leakage of 50pA and guaranteed break-before-
make operation. Charge injection is
±10pC
maximum. All
digital inputs are TTL and CMOS compatible when oper-
ated from single or dual supplies. The inputs can with-
stand 100mA fault current.
The LTC1391 is available in 16-pin PDIP, SSOP and
narrow SO packages. For applications requiring 2-way
serial data transmission, see the LTC1390 data sheet.
, LTC and LT are registered trademarks of Linear Technology Corporation.
Low R
ON
: 45Ω
Single 2.7V to
±5V
Supply Operation
Analog Inputs May Extend to Supply Rails
Low Charge Injection
Serial Digital Interface
Low Leakage:
±5nA
Max
Guaranteed Break-Before-Make
TTL/CMOS Compatible for All Digital Inputs
Cascadable to Allow Additional Channels
Can Be Used as a Demultiplexer
APPLICATIONS
s
s
s
Data Acquisition Systems
Communication Systems
Signal Multiplexing/Demultiplexing
TYPICAL APPLICATION
3V, 8-Channel 12-Bit ADC
0.1µF
OPTIONAL A/D
INPUT FILTER
3V
300
1
2
3
ANALOG
INPUTS
4
5
6
7
8
S0
S1
S2
S3
S4
S5
S6
S7
LTC1391
V
+
D
V
–
D
OUT
D
IN
CS
CLK
GND
DATA IN
CLK
CS
DATA OUT
16
15
14
13
12
11
10
9
1
2
3
4
V
REF
+IN
–IN
GND
V
CC
LTC1285
D
OUT
CS/SHDN
CLK
8
7
6
5
1µF
250
ON-RESISTANCE (Ω)
SERIAL INTERFACE
TO MUX AND ADC
1391 TA01
U
U
U
On-Resistance vs
Analog Input Voltage
T
A
= 25°C
V
+
= 2.7V
V
–
= 0V
200
150
100
50
V
+
= 5V
V
–
= –5V
0
–5 –4 –3 –2 –1 0 1 2 3
ANALOG INPUT VOLTAGE (V)
4
5
1391 TA02
1
LTC1391
ABSOLUTE
MAXIMUM
RATINGS
(Note 1)
PACKAGE/ORDER INFORMATION
TOP VIEW
S0 1
S1 2
S2 3
S3 4
S4 5
S5 6
S6 7
S7 8
16
V
+
Total Supply Voltage (V
+
to V
–
) .............................. 15V
Input Voltage
Analog Inputs ................... (V
–
– 0.3V) to (V
+
+ 0.3V)
Digital Inputs ......................................... – 0.3V to 15V
Digital Outputs ..........................– 0.3V to (V
+
+ 0.3V)
Power Dissipation.............................................. 500mW
Operating Temperature Range
LTC1391C ............................................... 0°C to 70°C
LTC1391I........................................... – 40°C to 85°C
Storage Temperature Range ................. – 65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
ORDER PART
NUMBER
LTC1391CGN
LTC1391CN
LTC1391CS
LTC1391IGN
LTC1391IN
LTC1391IS
GN PART MARKING
1391
1391I
15 D
14 V
–
13 D
OUT
12 D
IN
11 CS
10 CLK
9
GND
N PACKAGE
GN PACKAGE
16-LEAD PLASTIC SSOP 16-LEAD PDIP
S PACKAGE
16-LEAD PLASTIC SO
T
JMAX
= 125°C,
θ
JA
= 110°C/ W (GN)
T
JMAX
= 125°C,
θ
JA
= 70°C/ W (N)
T
JMAX
= 125°C,
θ
JA
= 100°C/ W (S)
Consult factory for Military grade parts.
V
+
= 5V, V
–
= – 5V, GND = 0V, T
A
= operating temperature range, unless otherwise specified.
SYMBOL PARAMETER
Switch
V
ANALOG
Analog Signal Range
R
ON
On-Resistance
CONDITIONS
(Note 2)
V
S
=
±3.5V
I
D
= 1mA
q
ELECTRICAL CHARACTERISTICS
MIN
–5
TYP
MAX
5
75
75
120
UNITS
V
Ω
Ω
Ω
%
%/°C
nA
nA
nA
nA
nA
nA
V
V
µA
V
V
V
MHz
ns
ns
ns
dB
pC
T
MIN
25°C
T
MAX
45
20
0.5
±0.05
q
I
S(OFF)
I
D(OFF)
I
D(ON)
Digital
V
INH
V
INL
I
INL
, I
INH
V
OH
V
OL
Dynamic
f
CLK
t
ON
t
OFF
t
OPEN
OIRR
Q
INJ
∆R
ON
vs V
S
∆R
ON
vs Temperature
Off Input Leakage
Off Output Leakage
On Channel Leakage
V
S
= 4V, V
D
= – 4V, V
S
= – 4V, V
D
= 4V
Channel Off
V
S
= 4V, V
D
= – 4V, V
S
= – 4V, V
D
= 4V
Channel Off
V
S
= V
D
=
±4V
Channel On
V
+
= 5.25V
V
+
= 4.75V
V
IN
= 5V, 0V
V
+
= 4.75V, I
O
= – 10µA
I
O
= – 360µA
+
= 4.75V, I = 1.6mA
V
O
(Note 2)
V
S
= 2.5V, R
L
= 1k, C
L
= 35pF
V
S
= 2.5V, R
L
= 1k, C
L
= 35pF
±0.05
q
±0.05
q
q
q
q
q
q
±5
±20
±5
±20
±5
±20
High Level Input Voltage
Low Level Input Voltage
Input Current
High Level Output Voltage
Low Level Output Voltage
Clock Frequency
Enable Turn-On Time
Enable Turn-Off Time
Break-Before-Make Interval
Off Isolation
Charge Injection
2.4
0.8
±5
2.4
4.74
4.50
0.5
0.8
5
400
200
35
V
S
= 2V
P–P
, R
L
= 1k, f = 100kHz
R
S
= 0, C
L
= 1000pF, V
S
= 1V (Note 2)
260
100
155
70
±2
±10
2
U
W
U
U
W W
W
LTC1391
ELECTRICAL CHARACTERISTICS
V
+
= 5V, V
–
= – 5V, GND = 0V, T
A
= operating temperature range, unless otherwise specified.
SYMBOL
Dynamic
C
S(OFF)
C
D(0FF)
Supply
I
+
I
–
PARAMETER
Input Off Capacitance
Output Off Capacitance
Positive Supply Current
Negative Supply Current
All Logic Inputs Tied Together, V
IN
= 0V or 5V
All Logic Inputs Tied Together, V
IN
= 0V or 5V
q
q
CONDITIONS
MIN
TYP
5
10
15
– 15
MAX
UNITS
pF
pF
40
– 40
µA
µA
V
+
= 2.7V, V
–
= GND = 0V, T
A
= operating temperature range, unless otherwise specified.
SYMBOL PARAMETER
Switch
V
ANALOG
Analog Signal Range
R
ON
On-Resistance
CONDITIONS
(Note 2)
V
S
= 1.2V
I
O
= 1mA
q
MIN
0
TYP
MAX
2.7
300
300
350
UNITS
V
Ω
Ω
Ω
%
%/°C
nA
nA
nA
nA
nA
nA
V
V
µA
V
V
V
V
MHz
ns
ns
ns
dB
pC
pF
pF
µA
T
MIN
25°C
T
MAX
250
20
0.5
±0.05
q
I
S(OFF)
I
D(OFF)
I
D(ON)
Digital
V
INH
V
INL
I
INL
, I
INH
V
OH
V
OL
Dynamic
f
CLK
t
ON
t
OFF
t
OPEN
QIRR
Q
INJ
C
S(OFF)
C
D(OFF)
Supply
I
+
∆R
ON
vs V
S
∆R
ON
vs Temperature
Off Input Leakage
Off Output Leakage
On Channel Leakage
V
S
= 2.5V, V
D
= 0.5V; V
S
= 0.5V, V
D
= 2.5V (Note 3)
Channel Off
V
S
= 2.5V, V
D
= 0.5V; V
S
= 0.5V, V
D
= 2.5V (Note 3)
Channel Off
V
S
= V
D
= 0.5V, 2.5V (Note 3)
Channel On
V
+
= 3.0V
V
+
= 2.4V
V
IN
= 2.7V, 0V
V
+
= 2.7V, I
O
= – 20µA
I
O
= – 400µA
+
= 2.7V, I = 20µA
V
O
I
O
= 400µA
(Note 2)
V
S
= 1.5V, R
L
= 1k, C
L
= 35pF (Note 4)
V
S
= 1.5V, R
L
= 1k, C
L
= 35pF (Note 4)
(Note 4)
V
S
= 2V
P–P
, R
L
= 1k, f = 100kHz
R
S
= 0, C
L
= 1000pF, V
S
= 1V (Note 2)
±0.05
q
±0.05
q
q
q
q
q
q
±5
±20
±5
±20
±5
±20
High Level Input Voltage
Low Level Input Voltage
Input Current
High Level Output Voltage
Low Level Output Voltage
2.0
0.8
±5
2.0
2.68
2.30
0.01
0.20
0.8
5
800
400
Clock Frequency
Enable Turn-On Time
Enable Turn-Off Time
Break-Before-Make Interval
Off Isolation
Charge Injection
Input Off Capacitance
Output Off Capacitance
Positive Supply Current
125
490
190
290
70
±1
5
10
0.2
±5
All Logic Inputs Tied Together, V
IN
= 0V or 2.7V
q
2
The
q
denotes specifications which apply over the full operating
temperature range.
Note 1:
Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2:
Guaranteed by Design.
Note 3:
Leakage current with a single 2.7V supply is guaranteed by
correlation with the
±5V
leakage current specifications.
Note 4:
Timing specifications with a single 2.7V supply are guaranteed by
correlation with the
±5V
timing specifications.
3
LTC1391
TYPICAL PERFORMANCE CHARACTERISTICS
On-Resistance vs Temperature
300
250
V
+
= 2.7V
V
–
= 0V
V
S
= 1.2V
200
150
100
50
0
–40
V
+
= 5V
V
–
= –5V
V
S
= 0V
OUTPUT VOLTAGE (V)
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
V
+
= 5V
V
–
= –5V
OUTPUT VOLTAGE (V)
ON-RESISTANCE (Ω)
–20
20
40
60
0
TEMPERATURE (°C)
Driver Output High Voltage
vs Output Current
0
–0.5
V
+
= 2.7V
V
–
= 0V
OUTPUT CURRENT (mA)
OUTPUT VOLTAGE (V)
–1.0
–1.5
–2.0
–2.5
–3.0
–3.5
–4.0
2.0
2.5
3.0
3.5
4.0
OUTPUT VOLTAGE (V)
T
A
=25°C
4.5
5.0
1391 G04
PIN FUNCTIONS
S0, S1, S2, S3, S4, S5, S6, S7 (Pins 1, 2, 3, 4, 5, 6, 7,
8):
Analog Multiplexer Inputs.
GND (Pin 9):
Digital Ground. Connect to system ground.
CLK (Pin 10):
System Clock (TTL/CMOS Compatible). The
clock synchronizes the channel selection bits and the
serial data transfer from D
IN
to D
OUT
.
CS (Pin 11):
Channel Select Input (TTL/CMOS Compat-
ible). A logic high on this input enables the LTC1391 to
read in the channel selection bits and allows digital data
transfer from D
IN
to D
OUT
. A logic low on this input puts
D
OUT
into three-state and enables the selected channel for
analog signal transmission.
D
IN
(Pin 12):
Digital Input (TTL/CMOS Compatible). Input
for the channel selection bits.
D
OUT
(Pin 13):
Digital Output (TTL/CMOS Compatible).
Output from the internal shift register.
V
–
(Pin 14):
Negative Supply.
D (Pin 15):
Analog Multiplexer Output.
V
+
(Pin 16):
Positive Supply.
4
U W
80
1391 G01
Driver Output Low Voltage
vs Output Current
1.2
1.1
1.0
0.9
T
A
= 25°C
V = 2.7V
V
–
= 0V
+
Driver Output Low Voltage
vs Temperature
0.65
0.60
0.55
0.50
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
–40
V
+
= 2.7V
V
–
= 0V
I
O
= 400µA
V
+
= 5V
V
–
= –5V
I
O
= 1.8mA
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
OUTPUT CURRENT (mA)
1391 G02
–20
40
60
0
20
TEMPERATURE (°C)
80
1391 G03
Driver Output High Voltage
vs Temperature
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
–40
–20
40
60
0
20
TEMPERATURE (°C)
80
1391 G05
V
+
= 5V
V
–
= –5V
I
O
= 1.6mA
V
+
= 5V
V
–
= –5V
V
+
= 2.7V
V
–
= 0V
I
O
= 400µA
U
U
U
LTC1391
APPLICATIONS INFORMATION
Multiplexer Operation
Figure 1 shows the block diagram of the components
within the LTC1391 required for MUX operation. The
LTC1391 uses D
IN
to select the active channel and the chip
select input, CS, to switch on the selected channel as
shown in Figure 2.
When CS is high, the input data on the D
IN
pin is latched
into the 4-bit shift register on the rising clock edge. The
input data consists of the “EN” bit and a string of three bits
for channel selection. If “EN” bit is logic high as illustrated
in the first input data sequence, it enables the selected
channel. After the clocking in of the last channel selection
bit B0, the CS pin must be pulled low before the next rising
clock edge to ensure correct operation. Once CS is pulled
low, the previously selected channel is switched off to
ensure a break-before-make interval. After a delay of t
ON
,
the selected channel is switched on allowing signal trans-
mission. The selected channel remains on until the next
falling edge of CS. After a delay of t
OFF
, the LTC1391
terminates the analog signal transmission and allows the
CLK
D
IN
CS
CONTROL
LOGIC
4-BIT SHIFT
REGISTER
ANALOG INPUTS
(S0 TO S7)
MUX
BLOCK
ANALOG
OUTPUT (D)
1391 • F01
Figure 1. Simplified Block Diagram of the MUX Operation
CLK
CS
D
IN
EN
HIGH
B2
B1
B0
ANY ANALOG
INPUT
D
t
ON
t
OFF
1391 • F02
Figure 2. Multiplexer Operation
U
W
U
U
selection of next channel. If the “EN” bit is logic low, as
illustrated in the second data sequence, it disables all
channels and there will be no analog signal transmission.
Table 1 shows the various bit combinations for channel
selection.
Table 1. Logic Table for Channel Selection
ACTIVE CHANNEL
All Off
S0
S1
S2
S3
S4
S5
S6
S7
EN
0
1
1
1
1
1
1
1
1
B2
X
0
0
0
0
1
1
1
1
B1
X
0
0
1
1
0
0
1
1
BO
X
0
1
0
1
0
1
0
1
Digital Data Transfer Operation
The block diagram of Figure 3 shows the components
within the LTC1391 required for serial data transfer. When
CS is held high, data is fed into the 4-bit shift register and
then shifted to D
OUT
. Data appears at D
OUT
after the fourth
rising edge of the clock as shown in Figure 4. The last four
CLK
D
IN
CS
CONTROL
LOGIC
4-BIT SHIFT
REGISTER
D
OUT
1391 F03
Figure 3. Simplified Block Diagram of the
Digital Data Transfer Operation
EN LO
B2
B1
B0
5
医疗电子
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
