HUF75545P3, HUF75545S3, HUF75545S3S
Data Sheet
September 2002
75A, 80V, 0.010 Ohm, N-Channel,
UltraFET
®
Power MOSFET
Packaging
JEDEC TO-220AB
SOURCE
DRAIN
GATE
GATE
SOURCE
DRAIN
(FLANGE)
JEDEC TO-263AB
DRAIN
(FLANGE)
Features
• Ultra Low On-Resistance
- r
DS(ON)
= 0.010Ω,
V
GS
=
10V
• Simulation Models
- Temperature Compensated PSPICE® and SABER™
Electrical Models
- Spice and SABER Thermal Impedance Models
- www.fairchildsemi.com
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
HUF75545P3
HUF75545S3S
JEDEC TO-262AA
SOURCE
DRAIN
DRAIN
(FLANGE)
GATE
HUF75545S3
Ordering Information
PART NUMBER
PACKAGE
TO-220AB
TO-262AA
TO-263AB
BRAND
75545P
75545S
75545S
HUF75545P3
Symbol
D
HUF75545S3
HUF75545S3S
G
NOTE: When ordering, use the entire part number. Add the suffix T to
obtain the TO-263AB variant in tape and reel, e.g., HUF75545S3ST.
S
Absolute Maximum Ratings
T
C
= 25
o
C, Unless Otherwise Specified
HUF75545P3, HUF75545S3,
HUF75545S3S
80
80
±20
75
73
Figure 4
Figure 6
270
1.8
-55 to 175
300
260
UNITS
V
V
V
A
A
Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
DSS
Drain to Gate Voltage (R
GS
= 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V
DGR
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
GS
Drain Current
Continuous (T
C
= 25
o
C, V
GS
= 10V) (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
D
Continuous (T
C
= 100
o
C, V
GS
= 10V) (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
D
Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
DM
Pulsed Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UIS
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P
D
Derate Above 25
o
C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
J
, T
STG
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
L
Package Body for 10s, See Techbrief TB334. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
pkg
NOTES:
1. T
J
= 25
o
C to 150
o
C.
W
W/
o
C
o
C
o
C
o
C
CAUTION:
Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Product reliability information can be found at http://www.fairchildsemi.com/products/discrete/reliability/index.html
For severe environments, see our Automotive HUFA series.
All Fairchild semiconductor products are manufactured, assembled and tested under ISO9000 and QS9000 quality systems certification.
©2002 Fairchild Semiconductor Corporation
HUF75545P3 / HUF75545S3 / HUF75545S3S Rev. C
HUF75545P3, HUF75545S3, HUF75545S3S
Electrical Specifications
PARAMETER
OFF STATE SPECIFICATIONS
Drain to Source Breakdown Voltage
Zero Gate Voltage Drain Current
BV
DSS
I
DSS
I
D
= 250µA, V
GS
= 0V (Figure 11)
V
DS
= 75V, V
GS
= 0V
V
DS
= 70V, V
GS
= 0V, T
C
= 150
o
C
Gate to Source Leakage Current
ON STATE SPECIFICATIONS
Gate to Source Threshold Voltage
Drain to Source On Resistance
THERMAL SPECIFICATIONS
Thermal Resistance Junction to Case
Thermal Resistance Junction to
Ambient
R
θJC
R
θJA
TO-220 and TO-263
-
-
-
-
0.55
62
o
C/W
o
C/W
T
C
= 25
o
C
,
Unless Otherwise Specified
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
80
-
-
-
-
-
-
-
-
1
250
±100
V
µA
µA
nA
I
GSS
V
GS
=
±20V
V
GS(TH)
r
DS(ON)
V
GS
= V
DS
, I
D
= 250µA (Figure 10)
I
D
= 75A, V
GS
= 10V (Figure 9)
2
-
-
0.0082
4
0.010
V
Ω
SWITCHING SPECIFICATIONS
(V
GS
= 10V)
Turn-On Time
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Turn-Off Time
GATE CHARGE SPECIFICATIONS
Total Gate Charge
Gate Charge at 10V
Threshold Gate Charge
Gate to Source Gate Charge
Gate to Drain “Miller” Charge
CAPACITANCE SPECIFICATIONS
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
C
ISS
C
OSS
C
RSS
V
DS
= 25V, V
GS
= 0V,
f = 1MHz
(Figure 12)
-
-
-
3750
1100
350
-
-
-
pF
pF
pF
Q
g(TOT)
Q
g(10)
Q
g(TH)
Q
gs
Q
gd
V
GS
= 0V to 20V
V
GS
= 0V to 10V
V
GS
= 0V to 2V
V
DD
= 40V,
I
D
= 75A,
I
g(REF)
= 1.0mA
(Figure 13)
-
-
-
-
-
195
105
6.8
15
43
235
125
8.2
-
-
nC
nC
nC
nC
nC
t
ON
t
d(ON)
t
r
t
d(OFF)
t
f
t
OFF
V
DD
= 40V, I
D
= 75A
V
GS
=
10V,
R
GS
= 2.5Ω
-
-
-
-
-
-
-
14
125
40
90
-
210
-
-
-
-
195
ns
ns
ns
ns
ns
ns
Source to Drain Diode Specifications
PARAMETER
Source to Drain Diode Voltage
SYMBOL
V
SD
I
SD
= 75A
I
SD
= 35A
Reverse Recovery Time
Reverse Recovered Charge
t
rr
Q
RR
I
SD
= 75A, dI
SD
/dt = 100A/µs
I
SD
= 75A, dI
SD
/dt = 100A/µs
TEST CONDITIONS
MIN
-
-
-
-
TYP
-
-
-
-
MAX
1.25
1.00
100
300
UNITS
V
V
ns
nC
©2002 Fairchild Semiconductor Corporation
HUF75545P3 / HUF75545S3 / HUF75545S3S Rev. C
HUF75545P3, HUF75545S3, HUF75545S3S
Typical Performance Curves
1.2
POWER DISSIPATION MULTIPLIER
1.0
I
D
, DRAIN CURRENT (A)
60
V
GS
= 10V
40
0.8
0.6
0.4
0.2
0
0
25
50
75
100
125
150
175
T
C
, CASE TEMPERATURE (
o
C)
0
80
20
25
50
75
100
125
150
175
T
C
, CASE TEMPERATURE (
o
C)
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE
TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPERATURE
2
1
THERMAL IMPEDANCE
Z
θJC
, NORMALIZED
DUTY CYCLE - DESCENDING ORDER
0.5
0.2
0.1
0.05
0.02
0.01
P
DM
t
1
SINGLE PULSE
t
2
NOTES:
DUTY FACTOR: D = t
1
/t
2
PEAK T
J
= P
DM
x Z
θJC
x R
θJC
+ T
C
10
-3
10
-2
t, RECTANGULAR PULSE DURATION (s)
10
-1
10
0
10
1
0.1
0.01
10
-5
10
-4
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
2000
T
C
= 25
o
C
FOR TEMPERATURES
ABOVE 25
o
C DERATE PEAK
CURRENT AS FOLLOWS:
I = I
25
V
GS
= 10V
175 - T
C
150
I
DM
, PEAK CURRENT (A)
1000
100
50
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
10
-4
10
-3
10
-2
t, PULSE WIDTH (s)
10
-1
10
0
10
1
10
-5
FIGURE 4. PEAK CURRENT CAPABILITY
©2002 Fairchild Semiconductor Corporation
HUF75545P3 / HUF75545S3 / HUF75545S3S Rev. C
HUF75545P3, HUF75545S3, HUF75545S3S
Typical Performance Curves
600
I
AS
, AVALANCHE CURRENT (A)
(Continued)
600
I
D
, DRAIN CURRENT (A)
If R = 0
t
AV
= (L)(I
AS
)/(1.3*RATED BV
DSS
- V
DD
)
If R
≠
0
t
AV
= (L/R)ln[(I
AS
*R)/(1.3*RATED BV
DSS
- V
DD
) +1]
STARTING T
J
= 25
o
C
100
100µs
100
10
OPERATION IN THIS
AREA MAY BE
LIMITED BY r
DS(ON)
SINGLE PULSE
T
J
= MAX RATED
T
C
= 25
o
C
1
10
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
1ms
10ms
STARTING T
J
= 150
o
C
1
100
200
10
0.001
0.01
0.1
1
10
t
AV
, TIME IN AVALANCHE (ms)
NOTE: Refer to Fairchild Application Notes AN9321 and AN9322.
FIGURE 5. FORWARD BIAS SAFE OPERATING AREA
FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING
CAPABILITY
150
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
V
DD
= 15V
150
V
GS
= 20V
V
GS
= 10V
I
D
, DRAIN CURRENT (A)
120
V
GS
= 7V
V
GS
= 6V
I
D,
DRAIN CURRENT (A)
120
90
90
V
GS
=5V
60
T
J
= 175
o
C
T
J
= 25
o
C
60
30
30
T
J
= -55
o
C
0
0
2
3
4
5
6
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
T
C
= 25
o
C
0
1
2
3
4
V
GS
, GATE TO SOURCE VOLTAGE (V)
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
FIGURE 7. TRANSFER CHARACTERISTICS
FIGURE 8. SATURATION CHARACTERISTICS
2.5
NORMALIZED DRAIN TO SOURCE
ON RESISTANCE
PULSE DURATION = 80µs V
GS
= 10V, I
D
= 75A
DUTY CYCLE = 0.5% MAX
2.0
NORMALIZED GATE
THRESHOLD VOLTAGE
1.2
V
GS
= V
DS
, I
D
= 250µA
1.0
1.5
0.8
1.0
0.6
0.5
-80
-40
0
40
80
120
160
200
T
J
, JUNCTION TEMPERATURE (
o
C)
0.4
-80
-40
0
40
80
120
160
200
T
J
, JUNCTION TEMPERATURE (
o
C)
FIGURE 9. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
FIGURE 10. NORMALIZED GATE THRESHOLD VOLTAGE vs
JUNCTION TEMPERATURE
©2002 Fairchild Semiconductor Corporation
HUF75545P3 / HUF75545S3 / HUF75545S3S Rev. C
HUF75545P3, HUF75545S3, HUF75545S3S
Typical Performance Curves
1.2
NORMALIZED DRAIN TO SOURCE
BREAKDOWN VOLTAGE
I
D
= 250µA
1.1
C, CAPACITANCE (pF)
(Continued)
10000
C
ISS
=
C
GS
+ C
GD
C
OSS
≅
C
DS
+ C
GD
1.0
1000
0.9
C
RSS
=
C
GD
V
GS
= 0V, f = 1MHz
0.1
1
10
80
0.8
-80
-40
0
40
80
120
160
200
T
J
, JUNCTION TEMPERATURE (
o
C)
100
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
FIGURE 11. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
10
V
GS
, GATE TO SOURCE VOLTAGE (V)
V
DD
= 40V
8
FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
6
4
WAVEFORMS IN
DESCENDING ORDER:
I
D
= 75A
I
D
= 35A
0
30
60
Q
g
, GATE CHARGE (nC)
90
120
2
0
NOTE: Refer to Fairchild Application Notes AN7254 and AN7260.
FIGURE 13. GATE CHARGE WAVEFORMS FOR CONSTANT GATE CURRENT
©2002 Fairchild Semiconductor Corporation
HUF75545P3 / HUF75545S3 / HUF75545S3S Rev. C
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