1CY M74 SP5 4/55
PRELIMINARY
CYM74BP54
CYM74P54/55
CYM74SP54/55
Intel® 82430NX Chipset
Level II Cache Module Family
Features
• Pin-compatible secondary cache module family
• Asynchronous (CYM74BP54), synchronous pipelined
(CYM74P54, CYM74P55), or synchronous
(CYM74SP54, CYM74SP55) configurations with pres-
ence and configuration detect pins
• Ideal for Intel® P54C-based systems with the 82430NX
(Neptune) chipset
• Operates at 60 and 66 MHz
• Uses cost-effective CMOS asynchronous SRAMs or
high-performance synchronous SRAMs
• 160-position Burndy DIMM CELP2X80SC3Z48
connector
• 3.3V inputs/outputs
dustry standard 5V SRAMs and 3.3V level translators for CPU
bus speeds up to 66 MHz. The CYM74BP54 is organized as
32K by 64-bits.
The synchronous modules are available with low-cost syn-
chronous pipelined RAMs or higher performance synchronous
burst RAMs. The synchronous pipelined modules are based
on a 16Kx64 RAM. The CYM74P54 is a 256-KB module while
the CYM74P55 is a 512-KB module. Both are modules without
byte parity.
The CYM74SP54 and CYM74SP55 are synchronous burst
cache modules that provide zero wait-state performance at a
bus speed of 66 MHz. The CYM74SP54 is a 256-Kbyte cache
module with byte parity. The CYM74SP55 is a 512-Kbyte
cache module with byte parity.
Multiple ground pins and on-board decoupling capacitors en-
sure high performance with maximum noise immunity.
All components on the cache modules are surface mounted
on a multi-layer epoxy laminate (multifunctional) substrate.
The contact pins are plated with 150 micro-inches of nickel
covered by 10 micro-inches of gold flash.
Functional Description
This family of secondary cache modules is designed for Intel
P54C systems with the 82430NX (Neptune) chipset.
CYM74BP54 is an asynchronous 256-Kbyte cache module
that provides a low-cost, high-performance solution with in-
Logic Block Diagram - CYM74BP54
A
17
-A
7
A
6–0
-A
5–
0
CALE
LE
ADDRESS LATCH
D
0
-D
7
D
8
-D
15
D
16
-D
23
D
24
-D
31
LA
17
-LA
5
32K x 8
D
32K x 8
D
A
CE
OE
WE
2
A
CE
OE
WE
3
32K x 8
D
32K x 8
D
A
CE
OE
WE
1
A
4–
-A
3–
0
0
A
CE
OE
WE
0
CE
0
OE
0
WE
0
-WE
3
D
32
-D
D
40
-D
D
48
-D
D
56
-D
39
47
55
63
32K x 8
D
A
CE
OE
WE
4
CE
1
OE
1
WE
4
-WE
7
Intel is a registered trademark of Intel Corporation.
32K x 8
D
A
CE
OE
WE
5
32K x 8
D
A
CE
OE
WE
6
32K x 8
D
A
CE
OE
WE
7
A
4–
-A
3–
1
1
74BP54–1
A
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134 •
408-943-2600
May 1994 – Revised October 1995
PRELIMINARY
Block Diagram: 5V to 3.3V Level Conversion (CYM74BP54)
5.0Volts
CYM74BP54
CYM74P54/55
CYM74SP54/55
100ohms
Vcc
4.3Vzener
5%tolerance
5VSRAM
64BitBusSwitch
(uses7CYBUS3384)
D
3.3VcompliantI/O
B
GND
BE
[2:1]
74BP54–2
Logic Block Diagram - CYM74P54, CYM74P55
CYM74P54
CYM74P55
CYM74P55ONLY
CLK1
CLK0
CK
D
A16 7
-A
A6– -A 3–
0
0
WE7-WE 0
ADSP0
ADSC0
ADV0
CE0
OE0
A
A
8
BE0-BE 7
ADSP
ADSC
ADV
CS0
OE
A
A
BE0-BE 7
ADSP
ADSC
ADV
CS 0
OE
CK
D
A
A
BE0-BE 7
ADSP
ADSC
ADV
CS 0
OE
CK
D
A
A
BE0-BE 7
ADSP
ADSC
ADV
CS0
OE
CK
D
PD2
TBD
TBD
PD1
TBD
TBD
PD0
TBD
TBD
D63 0
-D
A6– -A 3–
1
1
ADSP1
ADSC1
ADV1
CE1
OE1
CS1
CS2
CS4 VCC
CS3 VCC
GND CS 1
CS 2
CS 4
CS 3 VCC
CS 1
GND CS 2
CS 4 VCC
CS 3
GND CS1
GND CS2
CS4
CS3
A17
CYM74P54(GND)
CYM74P55 (A18)
16Kx64
16Kx64
16Kx64
16Kx64
74BP54–3
2
PRELIMINARY
Logic Block Diagram - CYM74SP54/CYM74SP55
CYM74BP54
CYM74P54/55
CYM74SP54/55
D
0
-D
15
DP
0
-DP
1
D
16
-D
31
DP
2
-DP
3
D
32
-D
47
DP
4
-DP
5
D
48
-D
63
DP
6
-DP
7
Note:A
18
isnotusedbyCYM74SP54
(CYM74SP54)32K x 18
(CYM74SP55)64Kx18
D
A
18
-A
7
A
6–
-A
3–
0
0
ADSP0
ADSC0
ADV0
A
ADSP
ADSC
ADV
CE
OE
WE0/1
CLK0
CLK1
CE
0
OE
0
CE
1
OE
1
WE
0
-WE
7
A
ADSP
ADSC
ADV
CE
OE
WE2/3
D
A
6–
-A
3–
A
1
1
ADSP1 ADSP
ADSC1 ADSC
ADV1 ADV
CE
OE
WE4/5
D
A
ADSP
ADSC
ADV
CE
OE
WE6/7
D
74BP54–4
Selection Guide
Asynchronous Cache Modules
Part Number
Cache Size (KB)
System Clock (MHz)
RAM Speed
60
t
AA
=15 ns
Synchronous Pipelined Cache Modules
Part Number
Cache Size (KB)
System Clock (MHz)
RAM Speed
60
t
CDV
=10.5 ns
CYM74P54-60
256
66
t
CDV
=8.5 ns
CYM74P54-66
CYM74P55-60
512
60
t
CDV
=10.5 ns
66
t
CDV
=8.5 ns
CYM74P55-66
CYM74BP54-60
256
66
t
AA
=12 ns
CYM74BP54-66
Synchornous Burst Cache Modules
Part Number
Cache Size (KB)
System Clock (MHz)
RAM Speed
60
t
CDV
=10.5 ns
CYM74SP54-60
256
66
t
CDV
=8.5 ns
CYM74SP54-66
CYM74SP55-60
512
60
t
CDV
=10.5 ns
66
t
CDV
=8.5 ns
CYM74SP55-66
3
PRELIMINARY
Pin Configuration
Dual Read–Out SIMM (DIMM)
Top View
GND
D
63
V
CC
D
61
V
CC
D
59
D
57
GND
(74P5X, 74SP5X) DP
7
/ (74BP54) NC
D
55
D
53
D
51
GND
D
49
D
47
D
45
D
43
GND
D
41
(74P5X, 74SP5X) DP
5
/ (74BP54) NC
D
39
D
37
D
35
GND
D
33
D
31
D
29
D
27
D
25
GND
(74P5X, 74SP5X) DP
3
/ (74BP54) NC
D
23
D
21
V
CC
D
19
GND
D
17
V
CC
D
15
D
13
GND
D
11
V
CC
D
9
(74P5X, 74SP5X) DP
1
/ (74BP54) NC
V
CC
D
7
D
5
D
3
D
1
GND
A
3–
1
A
4–
1
(74P5X, 74SP5X) A
5–
/ (74BP54) NC
1
(74P5X, 74SP5X) A
6–
/ (74BP54) NC
1
A
7
GND
A
9
A
11
A
13
A
15
A
17
GND
(ReservedA
19
) NC
PD1
(74P5X, 74SP5X) CLK0 / (74BP54) NC
(Reserved CLK2) NC
GND
WE
7
WE
5
WE
3
WE
1
GND
(74P55, 74SP5X) ADSC1 / (74BP54, 74P54) NC
CE
1
(74P55, 74SP5X) ADV1 / (74BP54, 74P54) NC
OE
1
V
CC
(74P55, 74SP5X) ADSP1 / (74BP54, 74P54) NC
GND
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
CYM74BP54
CYM74P54/55
CYM74SP54/55
GND
D
62
NC (74BP54) / V
CCQ
(74P5X, 74SP5X)
D
60
NC (74BP54) / V
CCQ
(74P5X, 74SP5X)
D
58
D
56
GND
NC (74BP54) / DP
6
(74P5X, 74SP5X)
D
54
D
52
D
50
GND
D
48
D
46
D
44
D
42
GND
D40
NC (74BP54) / DP
4
(74P5X, 74SP5X)
D
38
D
36
D
34
GND
D
32
D
30
D
28
D
26
D
24
GND
NC (74BP54) / DP
2
(74P5X, 74SP5X)
D
22
D
20
NC (74BP54) / V
CCQ
(74P5X, 74SP5X)
D
18
GND
D
16
NC (74BP54) / V
CCQ
(74P5X, 74SP5X)
D
14
D
12
GND
D
10
NC (74BP54) / V
CCQ
(74P5X, 74SP5X)
D
8
NC (74BP54) / DP
0
(74P5X, 74SP5X)
NC (74BP54) / V
CCQ
(74P5X, 74SP5X)
D
6
D
4
D
2
D
0
GND
A
3–
0
A
4–
0
A
5–
0
A
6–
0
A
8
GND
A
10
A
12
A
14
A
16
NC (74BP54, 74SP54) / GND (74P54) / A
18
(74P55, 74SP55)
GND
PD
0
PD
2
NC (74BP54, 74P54) / CLK1 (74P55, 74SP5X)
NC (Reserved CLK3)
GND
WE
6
WE
4
WE
2
WE
0
GND
CALE (74BP54) / ADSC0 (74P5X, 74SP5X)
CE
0
NC (74BP54) / ADV0 (74P5X, 74SP5X)
OE
0
NC (74BP54) / V
CCQ
(74P5X, 74SP5X)
NC (74BP54) / ADSP0 (74P5X, 74SP5X)
74BP54–5
GND
4
PRELIMINARY
Pin Definitions
Common Signals
V
CC
GND
A
7
–A
19
A
3–0
, A
4–0
A
3–1
, A
4–1
A
5–0
, A
6–0
CE
0
, CE
1
OE
0
, OE
1
WE
0
, WE
1
,WE
2
,WE
3
WE
4
,WE
5
,WE
6
,WE
7
PD
0
–PD
2
D
0
–D
63
NC
CYM74BP54 Only Signals
CALE
CYM74P5X, CYM74SP5X Signals
V
CCQ
DP
0
–DP
7
ADSP0, ADSP1
ADSC0,ADSC1
ADV0, ADV1
A
5–1
, A
6–1
CLK0, CLK1, CLK2, CLK3
3.3V Supply
Data Parity lines (Optional)
Processor Address Strobe, ADSP1 not used on CYM74P54
Latch Enable
Description
5V Supply
Ground
Addresses from processor
Description
CYM74BP54
CYM74P54/55
CYM74SP54/55
Lower address from chipset, identical to the bank1 addresses
Lower address from chipset, identical to the bank0 addresses, A
3-1
, A
4-1
not used on
CYM74P54
Lower address from processor (CYM74P5X, CYM74SP5X- identical to the bank1
addresses)
Chip Enable (same signal), CE
1
not used on CYM74P54
Output Enable (same signal), OE
1
not used on CYM74P54
Byte Write Enables
Presence Detect pins
Data lines from processor
Signal not connected on module.
Description
Cache Controller Address Strobe, ADSC1 not used on CYM74P54
Burst Address Advance, ADV1 not used on CYM74P54
Lower address from processor, identical to the bank0 addresses, A
5-1
, A
6-1
not used on
CYM74P54
Clock signals (each should be given own clk driver); CLK0 used on CYM74P5X,
CYM74SP5X; CLK1 not used on CYM74P54; CLK2 and CLK3 are RSVD
Presence Detect Pins
PD
2
Asynchronous – CYM74BP54
Synchronous Pipelined – CYM74P54
Synchronous Pipelined – CYM74P55
Synchronous Burst – CYM74SP54
Synchronous Burst – CYM74SP55
NC
TBD
TBD
GND
GND
PD
1
GND
TBD
TBD
GND
GND
PD
0
NC
TBD
TBD
NC
GND
5